Nondeterministic Auxiliary Depth-Bounded Storage Automata and Semi-Unbounded Fan-in Cascading Circuits

TL;DR

The paper addresses the complexity of nondeterministic auxiliary depth-$k$ storage automata ($k$-sna) and introduces a semi-unbounded fan-in cascading circuit model to capture their power. It proves a tight circuit characterization: $ ext{AuxSNA depth-space-time}(2k,O( obreak \log n),n^{O(1)})_{FBS}$ equals $ ext{CCIRcasc, obreak alt, obreak size}(k,O( obreak log n),n^{O(1)})$, linking nondeterministic storage automata to circuit families with cascading blocks built from AND$_{(omega)}$, CAND, and COR gates under frozen-blank sensitivity. By relaxing the cascading constraint, it also shows a characterization of $ ext{P}$ and derives that $ ext{LOG}k ext{SNA}_{FBS}$ lies within $ ext{P}$; accordingly, an upper bound on the complexity of $ ext{LOG}k ext{SNA}$ is established. Overall, the work unifies storage-automata models with circuit-based parallelism, providing a time-space tradeoff perspective for log-space reductions and enriching the understanding of how nondeterministic storage interacts with circuit depth and width in a uniform framework.

Abstract

We discuss a nondeterministic variant of the recently introduced machine model of deterministic auxiliary depth-$k$ storage automata (or aux-$k$-sda's) by Yamakami. It was proven that all languages recognized by polynomial-time logarithmic-space aux-$k$-sda's are located between $\mathrm{LOGDCFL}$ and $\mathrm{SC}^k$ (the $k$th level of Steve's class SC). We further propose a new and simple computational model of semi-unbounded fan-in Boolean circuits composed partly of cascading blocks, in which the first few AND gates of unbounded fan-out (called AND$_{(ω)}$ gates) at each layer from the left (where all gates at each layer are indexed from left to right) are linked in a "cascading" manner to their right neighbors though specific AND and OR gates. We use this new circuit model to characterize a nondeterministic variant of the aux-$2k$-sda's (called aux-$2k$-sna's) that run in polynomial time using logarithmic work space. By relaxing the requirement for cascading circuits, we also demonstrate how such cascading circuit families characterize the complexity class $\mathrm{P}$. This yields an upper bound on the computational complexity of $\mathrm{LOG}k\mathrm{SNA}$ by $\mathrm{P}$.

Figures (10)

• Figure 1: Movement of $M$'s storage-tape head along a fixed computation path of $M$ on input $x$ with $k=4$, where each lattice point indicates a surface configuration at section time $t$ and is referred to as $C_t$. A section time means the number of steps by merging a consecutive series of all stationary moves of the storage-tape head into a non-stationary move that precedes the series. For example, the storage-tape head in $C_2,C_9,C_{11},C_{18}$ scans cells $2,5,3,4$, respectively. Cell 4 is visited by the tape head in $C_4,C_{10},C_{12},C_{14},C_{18}$, etc. The black circles indicate that the storage-tape cells are frozen with the frozen blank symbol $B$. For example, $C_{17},C_{23},C_{26}$ contain frozen blank tape cells.
• Figure 2: A construction of $N$. An input tape is omitted in this illustration. The current tape symbol of a $k$-sda $N$ is $[T_u,a,\varnothing]$ and $N$'s current inner state is $(T_w,q,+1)$ in (1). Two possible transitions of $N$ at the next step, depending on the value of $depth(a)$, are depicted in (2) and (3).
• Figure 3: Another construction of $N$. The $k$-sda $N$ is scanning $[\varnothing,a,T_v]$ with inner state $(q,+1)$ or $(T_w,q,+1)$ in (1). Two possible moves of $N$ are depicted in (2) and (3).
• Figure 4: A tree-like structure that represents the transitional relationships of all surface configuration duos corresponding to the movement depicted in Fig. \ref{['fig:storage-tape-head-move']}. A configuration duo inside a blue box indicates that its currently-scanned storage-tape cells are all frozen blank. A green dotted line indicates a link between two configuration duos. Here, the node $(C_{12},C_{14},2)$ depends on $(C_{13},C_{13},0)$ and $(C_{12},C_{14},C_{18},2,4)$, which is linked from $(C_{4},C_{10},6)$, and $(C_{16},C_{16},0)$ depends on $(C_{15},C_{17},2)$ and also it is linked from $(C_6,C_{8},2)$. On the contrary, $(C_{15},C_{17},2)$ depends only on $(C_{14},C_{18},4)$ and $(C_{16},C_{16},0)$ but is not linked from $(C_{13},C_{13},0)$ because the storage tape cells of $(C_{15},C_{17},2)$ are already frozen blank.
• Figure 5: A cascading block, which is a subcircuit composed of AND$_{(\omega)}$, CAND, and COR gates marked as large circles. The smaller circles at layers $1$ and $9$ indicate output gates and input gates of this subcircuit, respectively. The link length of this subcircuit is $3$. The numbers adjacent to some circles indicate gate labels. For example, gate 4 as well as gates $5$ and $6$ is linked to gate 2, which is further linked to gate 1. In contrast, gates $5$ and $7$ are not linked. Similarly, gates $5$ and $6$ are not linked.

Theorems & Definitions (18)

• Definition 2.1
• Lemma 2.3
• Corollary 2.4
• Lemma 2.5
• Definition 2.6
• Lemma 3.1
• Lemma 3.2
• Lemma 3.3
• Lemma 3.4
• Lemma 3.5