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Enhancing CGRA Efficiency Through Aligned Compute and Communication Provisioning

Zhaoying Li, Pranav Dangi, Chenyang Yin, Thilini Kaushalya Bandara, Rohan Juneja, Cheng Tan, Zhenyu Bai, Tulika Mitra

TL;DR

This work tackles overprovisioning of CGRA communication resources at edge scales by aligning compute and communication through motif-based hierarchical execution. It introduces Plaid, a co-designed CGRA architecture and compiler that identify recurrent three-node dataflow motifs, execute them within Plaid Collective Units (PCUs), and route data with a hierarchical NoC. Key contributions include the identification of a minimal, reusable three-node motif, a PCU design with local collect routing, a motif-aware compiler with hierarchical mapping, and domain-specialized optimization pathways. Empirical results show Plaid achieves up to 43% power reduction and 46% area reduction versus a baseline spatio-temporal CGRA, while delivering 1.40× performance and 48% area savings versus a spatial CGRA, signaling strong practical impact for energy-constrained edge accelerators.

Abstract

Coarse-grained Reconfigurable Arrays (CGRAs) are domain-agnostic accelerators that enhance the energy efficiency of resource-constrained edge devices. The CGRA landscape is diverse, exhibiting trade-offs between performance, efficiency, and architectural specialization. However, CGRAs often overprovision communication resources relative to their modest computing capabilities. This occurs because the theoretically provisioned programmability for CGRAs often proves superfluous in practical implementations. In this paper, we propose Plaid, a novel CGRA architecture and compiler that aligns compute and communication capabilities, thereby significantly improving energy and area efficiency while preserving its generality and performance. We demonstrate that the dataflow graph, representing the target application, can be decomposed into smaller, recurring communication patterns called motifs. The primary contribution is the identification of these structural motifs within the dataflow graphs and the development of an efficient collective execution and routing strategy tailored to these motifs. The Plaid architecture employs a novel collective processing unit that can execute multiple operations of a motif and route related data dependencies together. The Plaid compiler can hierarchically map the dataflow graph and judiciously schedule the motifs. Our design achieves a 43% reduction in power consumption and 46% area savings compared to the baseline high-performance spatio-temporal CGRA, all while preserving its generality and performance levels. In comparison to the baseline energy-efficient spatial CGRA, Plaid offers a 1.4x performance improvement and a 48% area savings, with almost the same power.

Enhancing CGRA Efficiency Through Aligned Compute and Communication Provisioning

TL;DR

This work tackles overprovisioning of CGRA communication resources at edge scales by aligning compute and communication through motif-based hierarchical execution. It introduces Plaid, a co-designed CGRA architecture and compiler that identify recurrent three-node dataflow motifs, execute them within Plaid Collective Units (PCUs), and route data with a hierarchical NoC. Key contributions include the identification of a minimal, reusable three-node motif, a PCU design with local collect routing, a motif-aware compiler with hierarchical mapping, and domain-specialized optimization pathways. Empirical results show Plaid achieves up to 43% power reduction and 46% area reduction versus a baseline spatio-temporal CGRA, while delivering 1.40× performance and 48% area savings versus a spatial CGRA, signaling strong practical impact for energy-constrained edge accelerators.

Abstract

Coarse-grained Reconfigurable Arrays (CGRAs) are domain-agnostic accelerators that enhance the energy efficiency of resource-constrained edge devices. The CGRA landscape is diverse, exhibiting trade-offs between performance, efficiency, and architectural specialization. However, CGRAs often overprovision communication resources relative to their modest computing capabilities. This occurs because the theoretically provisioned programmability for CGRAs often proves superfluous in practical implementations. In this paper, we propose Plaid, a novel CGRA architecture and compiler that aligns compute and communication capabilities, thereby significantly improving energy and area efficiency while preserving its generality and performance. We demonstrate that the dataflow graph, representing the target application, can be decomposed into smaller, recurring communication patterns called motifs. The primary contribution is the identification of these structural motifs within the dataflow graphs and the development of an efficient collective execution and routing strategy tailored to these motifs. The Plaid architecture employs a novel collective processing unit that can execute multiple operations of a motif and route related data dependencies together. The Plaid compiler can hierarchically map the dataflow graph and judiciously schedule the motifs. Our design achieves a 43% reduction in power consumption and 46% area savings compared to the baseline high-performance spatio-temporal CGRA, all while preserving its generality and performance levels. In comparison to the baseline energy-efficient spatial CGRA, Plaid offers a 1.4x performance improvement and a 48% area savings, with almost the same power.

Paper Structure

This paper contains 24 sections, 19 figures, 2 tables, 2 algorithms.

Table of Contents

  1. Introduction
  2. Background And Motivation
  3. Hierarchical Execution with Motifs
  4. Collective Routing
  5. Three-node Structural Motif
  6. Plaid Architecture
  7. Plaid PCU
  8. Hierarchical Network-on-Chip
  9. Configuration
  10. Efficient Domain-Specialization
  11. Plaid Compiler
  12. Mapping Problem Formulation
  13. Mapping DFG onto CGRA
  14. Experimental Methodology
  15. Architecture Synthesis
  16. ...and 9 more sections

Figures (19)

  • Figure 1: Overview of Plaid co-designed architecture and compiler
  • Figure 2: Power distribution for Plaid and a current state-of-the-art spatio-temporal CGRA. Plaid's execution paradigm reduces CGRA fabric power by 43% while maintaining performance and generality.
  • Figure 3: Spatio-temporal CGRA example
  • Figure 4: Example of a DFG corresponding to an annotated C code
  • Figure 5: Detailed routing example of the highlighted sub-DFG in Figure \ref{['fig:motivation_dfg']} on the 2$\times$2 CGRA from Figure \ref{['fig:motivation_cgra']}.
  • ...and 14 more figures