Bootstrapping, autonomous testing, and initialization system for Si/Si$_x$Ge$_{1-x}$ multi-quantum-dot devices

TL;DR

This work tackles the calibration bottleneck in scalable spin-qubit devices caused by trapped charges that shift gate thresholds and complicate autotuning. It introduces BATIS, a physics-informed, configuration-driven framework that autonomously boots, tests, and initializes gate-defined silicon/germanium quantum dot arrays, including a novel 1D current-channel formation strategy executed via a single 2D gate-sweep. The approach is demonstrated at 1.3 K on a four-quantum-dot Si/Si$_x$Ge$_{1-x}$ device, showing reliable leakage screening, global turn-on, channel isolation, and multi-channel formation without full millikelvin cooling. BATIS is platform-agnostic, scalable, and capable of recovering from trapped-charge disorder through gate-bias illumination, offering a practical pathway toward automated, large-scale QD qubit implementations and enabling pre-screening before deeper cryogenic operation. Together, these contributions provide a robust baseline for autonomous autotuning and a versatile tool for accelerating the deployment of large QD qubit arrays.

Abstract

Semiconductor quantum dot (QD) devices have become central to advancements in spin-based quantum computing. However, the increasing complexity of modern QD devices makes calibration and control -- particularly at elevated temperatures -- a bottleneck to progress, highlighting the need for robust and scalable autonomous solutions. A major hurdle arises from trapped charges within the oxide layers, which induce random offset voltage shifts on gate electrodes, with a standard deviation of approximately 83 mV of variation within state-of-the-art present-day devices. Efficient characterization and tuning of large arrays of QD qubits depend on choices of automated protocols. Here, we introduce a physically intuitive framework for a bootstrapping, autonomous testing, and initialization system (BATIS) designed to streamline QD device evaluation and calibration. BATIS navigates high-dimensional gate voltage spaces, automating essential steps such as leakage testing, formation of all current channels, and gate characterization in the presence of trapped charges. For forming the current channels, BATIS follows a non-standard approach that requires a single set of measurements regardless of the number of channels. Demonstrated at 1.3 K on a quad-QD Si/Si$_x$Ge$_{1-x}$ device, BATIS eliminates the need for deep cryogenic environments during initial device diagnostics, significantly enhancing scalability and reducing setup times. By requiring only minimal prior knowledge of the device architecture, BATIS represents a platform-agnostic solution, adaptable to various QD systems, which bridges a critical gap in QD autotuning.

Figures (6)

• Figure 1: (a) False-color scanning electron microscopy image of a device nominally identical to one used in this work. The color indicates the gate's function as a screening (S$_1$-S$_4$; yellow), reservoir (R$_1$-R$_5$; blue), barrier (B$_1$-B$_9$; gray), or plunger (P$_1$-P$_6$; red) gate. (b) Higher-magnification image with the desired current paths shown by black arrows and the individual barrier and plunger gates labeled. (c-f) Self-consistent Schrödinger-Poisson simulations (density plots), showing typical effects of trapped charge on 1D channel formation in a 2DEG. The simulation results are overlaid on the scanning electron microscopy image. (c) Trapped charge can lead to current paths crossing the central screening gate; an autotuner must detect and correct for this problem, as shown in (d). (e) Trapped charge can also lead to breaks in the current paths, another possible error that an autotuner must detect and correct for, as shown in (f). The insets in (c)--(f) show the gate voltages necessary to cause the charge densities. For all simulations, interface trapped charge is chosen, as described in the main text and in the Supplemental Material supp.
• Figure 2: BATIS algorithm. The flowchart representation of the procedural flow of BATIS. Beyond manipulating gate voltages, BATIS can also change the device response to gate voltages in situ by illuminating the device. Active steps in autotuning are shown by rounded gray rectangles, conditional logic is shown by yellow diamonds, and failure determinations are shown by red stop signs. The green and red arrows indicate whether a given step passes or fails, respectively.
• Figure 3: Stages of the tuning procedure. The first row in (a)--(d) explains the measurements. The second row shows idealized cartoon representations of the key data for each stage of the tuning process, with good and bad data shown on the left and the right, respectively. The third row provides examples of experimental data. The yellow arrows in the cartoons indicate the ideal current paths. (a) In the leakage test, no gate should have a low resistance to any other gate or cryostat ground (Ohmic contacts are included in the test for the nonaccumulated leakage test). The good cartoon matrix shows high-resistance paths on all connections. The bad cartoon matrix shows two gates shorted to each other. The realistic matrix shows three gates shorted to ground. Devices with shorted gates are typically unusable. (b) When accumulating the 2DEG in the device globally, the current is expected to rise above zero with the increase of gate voltages, as seen in the good cartoon plot. The bad cartoon plot shows a failure to turn on. A sccessful turn-on is observed in the experimental data, with G representing $\{{\rm S}_1, {\rm S}_3, {\rm S}_4, {\rm R}_1, {\rm R}2, {\rm R}3, {\rm R}4, {\rm R}5\}$ set of gates. (c) For pinch-off, it is desirable for the current to drop to the noise floor as the gate voltage is lowered. The bad cartoon demonstrates a failure of the screening or reservoir gate to pinch off. The experimental data show some small oscillations due to, for example, accidental Coulomb blockade during pinch-off. (d) For channel accumulation, rather than relying on measuring pairs of screening gates, we sweep a single screening gate against all the finger gates corresponding to that current channel. The bad cartoon measurement indicates that at least one finger gate is too far below the threshold to accumulate. (e) Each plunger and barrier gate must pinch off individually. The bad cartoon shows the finger gate failing to pinch off. In the experimental data, Coulomb blockade oscillations are often observed and are particularly prominent during pinch-off at this tuning step.
• Figure 4: Interplay between screening and finger gates during the single channel formation. (a) Current continuity simulation and (b) an example of an experimentally acquired $I$-$V$ response landscape in the screening gate vs finger gate space. (c) Schrödinger-Poisson simulated example showing three different operation modes, with each current channel programmed to be at a different operation mode: I, a proper 1D channel; II, an improper 2D channel under the screening and finger gates; III, an improper 2D channel under the screening gate. (d) Schrödinger-Poisson simulated example of the proper channel formation operation point for the device. Details about simulations are given in Supplemental Material supp.
• Figure 5: Example gate-voltage configurations determined by BATIS during tuning. The color value indicates the inferred gate voltage, with gates not analyzed at a given stage marked in gray. The color bar applies to all panels. (a) Global accumulation. The colors indicate the pinch-off voltages for the reservoir gates. (b) Screening and reservoir characterization. The reservoir gates are placed at their operating point, and the exterior screening gates are set to their pinch-off point. The central screening gate is set to the guaranteed isolation point. (c) Channel accumulation. The finger and screening gates are adjusted to the operating point. (d) The device’s final configuration, with the pinch-offs of all the finger gates colored.