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Sequential Printed MLP Circuits for Super TinyML Multi-Sensory Applications

Gurol Saglam, Florentia Afentaki, Georgios Zervakis, Mehdi B. Tahoori

TL;DR

This work tackles deploying large, multi-parameter neural networks on Printed Electronics by introducing sequential Super-TinyML circuits that combine single-cycle and multi-cycle neurons. It achieves substantial hardware reductions through pow2 quantization, multiplexed weight hardwiring, and architectural choices that replace shifting registers with multiplexers, enabling up to $753$ inputs and $8505$ coefficients (i.e., $35.9\times$ more features and $65.4\times$ more coefficients than prior PE solutions). The framework integrates redundant feature pruning and neuron approximation (via leading-$1$ bits and NSGA-II optimization) to further shrink area and power while maintaining accuracy, with thorough empirical validation across multiple UCI datasets. Overall, the results demonstrate that bespoke sequential designs can significantly push the feasibility of large-scale MLPs in PE, offering practical benefits for ultra-low-power, multi-sensory wearables and implants.

Abstract

Super-TinyML aims to optimize machine learning models for deployment on ultra-low-power application domains such as wearable technologies and implants. Such domains also require conformality, flexibility, and non-toxicity which traditional silicon-based systems cannot fulfill. Printed Electronics (PE) offers not only these characteristics, but also cost-effective and on-demand fabrication. However, Neural Networks (NN) with hundreds of features -- often necessary for target applications -- have not been feasible in PE because of its restrictions such as limited device count due to its large feature sizes. In contrast to the state of the art using fully parallel architectures and limited to smaller classifiers, in this work we implement a super-TinyML architecture for bespoke (application-specific) NNs that surpasses the previous limits of state of the art and enables NNs with large number of parameters. With the introduction of super-TinyML into PE technology, we address the area and power limitations through resource sharing with multi-cycle operation and neuron approximation. This enables, for the first time, the implementation of NNs with up to $35.9\times$ more features and $65.4\times$ more coefficients than the state of the art solutions.

Sequential Printed MLP Circuits for Super TinyML Multi-Sensory Applications

TL;DR

This work tackles deploying large, multi-parameter neural networks on Printed Electronics by introducing sequential Super-TinyML circuits that combine single-cycle and multi-cycle neurons. It achieves substantial hardware reductions through pow2 quantization, multiplexed weight hardwiring, and architectural choices that replace shifting registers with multiplexers, enabling up to inputs and coefficients (i.e., more features and more coefficients than prior PE solutions). The framework integrates redundant feature pruning and neuron approximation (via leading- bits and NSGA-II optimization) to further shrink area and power while maintaining accuracy, with thorough empirical validation across multiple UCI datasets. Overall, the results demonstrate that bespoke sequential designs can significantly push the feasibility of large-scale MLPs in PE, offering practical benefits for ultra-low-power, multi-sensory wearables and implants.

Abstract

Super-TinyML aims to optimize machine learning models for deployment on ultra-low-power application domains such as wearable technologies and implants. Such domains also require conformality, flexibility, and non-toxicity which traditional silicon-based systems cannot fulfill. Printed Electronics (PE) offers not only these characteristics, but also cost-effective and on-demand fabrication. However, Neural Networks (NN) with hundreds of features -- often necessary for target applications -- have not been feasible in PE because of its restrictions such as limited device count due to its large feature sizes. In contrast to the state of the art using fully parallel architectures and limited to smaller classifiers, in this work we implement a super-TinyML architecture for bespoke (application-specific) NNs that surpasses the previous limits of state of the art and enables NNs with large number of parameters. With the introduction of super-TinyML into PE technology, we address the area and power limitations through resource sharing with multi-cycle operation and neuron approximation. This enables, for the first time, the implementation of NNs with up to more features and more coefficients than the state of the art solutions.

Paper Structure

This paper contains 19 sections, 1 equation, 8 figures, 1 table, 1 algorithm.

Table of Contents

  1. Introduction
  2. Background on Printed Electronics
  3. Proposed Sequential Super-TinyMLs
  4. Proposed Sequential Architecture
  5. Multi-cycle neuron architecture
  6. Single-cycle neuron architecture
  7. Overview of the overall Super-TinyML architecture
  8. Architectural Choices
  9. Extraction of Model Parameters
  10. Quantization
  11. Redundant Feature Pruning
  12. Neuron Approximation
  13. Results
  14. Experimental Setup
  15. Evaluation of the Sequential Super-TinyMLs
  16. ...and 4 more sections

Figures (8)

  • Figure 1: Printed Electronics fabrication techniques.
  • Figure 2: Neuron architectures of a) the state-of-the-art Mubarik:MICRO:2020:printedml and proposed: b) multi-cycle neuron, c) single-cycle neuron.
  • Figure 3: Overview of the sequential super-TinyML architectures: a) state-of-the-art Mubarik:MICRO:2020:printedml, b) proposed.
  • Figure 4: Area comparison of registers vs. multiplexers.
  • Figure 5: The proposed neuron approximation using the leading-1 of the average expected products.
  • ...and 3 more figures