HiVeGen -- Hierarchical LLM-based Verilog Generation for Scalable Chip Design
Jinwei Tang, Jiayin Qin, Kiran Thorat, Chen Zhu-Tian, Yu Cao, Yang, Zhao, Caiwen Ding
TL;DR
HiVeGen tackles the challenge of scaling LLM-based Verilog generation for DSAs by introducing a hierarchical generation framework that decomposes designs into submodules and couples Design Space Exploration with a hierarchy-aware prompt strategy, a real-time on-the-fly parser, and a weight-based code retrieval system. The three-engine framework enables topology-aware prompts, real-time structural feedback, and reusable code blocks, reducing token usage and correction effort. Experimental results across simple designs and DSAs show improvements in generation accuracy and substantial token (up to 30.97%) and time savings (up to 45%), with PPA-aware configurations enabling optimized accelerator designs. The work demonstrates the practical impact of hierarchy, code reuse, and interactive correction in producing high-quality, scalable HDL designs with LLMs.
Abstract
With Large Language Models (LLMs) recently demonstrating impressive proficiency in code generation, it is promising to extend their abilities to Hardware Description Language (HDL). However, LLMs tend to generate single HDL code blocks rather than hierarchical structures for hardware designs, leading to hallucinations, particularly in complex designs like Domain-Specific Accelerators (DSAs). To address this, we propose HiVeGen, a hierarchical LLM-based Verilog generation framework that decomposes generation tasks into LLM-manageable hierarchical submodules. HiVeGen further harnesses the advantages of such hierarchical structures by integrating automatic Design Space Exploration (DSE) into hierarchy-aware prompt generation, introducing weight-based retrieval to enhance code reuse, and enabling real-time human-computer interaction to lower error-correction cost, significantly improving the quality of generated designs.