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SPICE-PIDE: A Methodology for Design and Optimization of Integrated Circuits

Jehan Taraporewalla, Arun KP, Sugata Ghosh, Abhishek Agarwal, Bijaydoot Basak, Dipankar Saha

TL;DR

The study addresses the challenge of optimizing IC parameters under trade-offs among power, speed, and noise by introducing a Python-based SPICE-PIDE interface to explore large design spaces. Using LTspice with a 22 nm PTM model, it optimizes two 5-transistor level-converter architectures (NNPT and PNPT) across nearly 1.84 million configurations and dual-supply settings, evaluating metrics such as VSwing, PAvg, and PDP. Results show substantial improvements in average power and PDP for both converters, with NNPT achieving about 26.6 nW PAvg and 8.5–8.7 aJ PDP, and PNPT achieving ~36–37 nW PAvg with ~20 aJ PDP, while maintaining complete voltage swing and minimal area impact. The findings demonstrate that SPICE-PIDE can efficiently yield diverse, high-quality design options suitable for ultra-low-power IC design within standard toolchains.

Abstract

In application-specific designs, owing to the trade-off between power consumption and speed, optimization of various circuit parameters has become a challenging task. Several of the performance metrics, viz. energy efficiency, gain, performance, and noise immunity, are interrelated and difficult to tune. Such efforts may result in a great deal of manual iterations which in turn increase the computational overhead. Thus, it is important to develop a methodology that not only explores large design space but also reduces the computational time. In this work, we investigate the viability of using a SPICE and Python IDE (PIDE) interface to optimize integrated circuits. The SPICE simulations are carried out using 22 nm technology node with a nominal supply voltage of 0.8 V. The SPICE-PIDE optimizer, as delineated in this work, is able to provide the best solution sets considering various performance metrics and design complexities for 5 transistor level converters.

SPICE-PIDE: A Methodology for Design and Optimization of Integrated Circuits

TL;DR

The study addresses the challenge of optimizing IC parameters under trade-offs among power, speed, and noise by introducing a Python-based SPICE-PIDE interface to explore large design spaces. Using LTspice with a 22 nm PTM model, it optimizes two 5-transistor level-converter architectures (NNPT and PNPT) across nearly 1.84 million configurations and dual-supply settings, evaluating metrics such as VSwing, PAvg, and PDP. Results show substantial improvements in average power and PDP for both converters, with NNPT achieving about 26.6 nW PAvg and 8.5–8.7 aJ PDP, and PNPT achieving ~36–37 nW PAvg with ~20 aJ PDP, while maintaining complete voltage swing and minimal area impact. The findings demonstrate that SPICE-PIDE can efficiently yield diverse, high-quality design options suitable for ultra-low-power IC design within standard toolchains.

Abstract

In application-specific designs, owing to the trade-off between power consumption and speed, optimization of various circuit parameters has become a challenging task. Several of the performance metrics, viz. energy efficiency, gain, performance, and noise immunity, are interrelated and difficult to tune. Such efforts may result in a great deal of manual iterations which in turn increase the computational overhead. Thus, it is important to develop a methodology that not only explores large design space but also reduces the computational time. In this work, we investigate the viability of using a SPICE and Python IDE (PIDE) interface to optimize integrated circuits. The SPICE simulations are carried out using 22 nm technology node with a nominal supply voltage of 0.8 V. The SPICE-PIDE optimizer, as delineated in this work, is able to provide the best solution sets considering various performance metrics and design complexities for 5 transistor level converters.

Paper Structure

This paper contains 5 sections, 4 figures, 4 tables.

Table of Contents

  1. Introduction
  2. Methodology
  3. Results
  4. Conclusion
  5. Acknowledgements

Figures (4)

  • Figure 1: Architecture of 5 transistor level converters (a) NNPT and (b) PNPT with the transistor sizing of 40nm/40nm for MP2 and load of 5 fF. The VddH and VddL values are 0.8 V and 0.6 V respectively NNPT.
  • Figure 2: Pseudo code for optimization of NNPT LC using SPICE-PIDE.
  • Figure 3: Pseudo code for optimization of PNPT LC using SPICE-PIDE.
  • Figure 4: Flow diagram illustrating the design optimization of 5 transistor level converters.