DRC-Coder: Automated DRC Checker Code Generation Using LLM Autonomous Agent

TL;DR

The paper tackles the onerous task of developing integrated DRC checkers for new technology nodes by introducing DRC-Coder, a multi-agent, vision-enabled framework that automates DRC code generation. It splits the workflow into interpretation and coding across two specialized LLMs (Planner and Programmer) and leverages three domain-specific tools to analyze rules, inspect layouts, and auto-evaluate generated code, enabling iterative debugging. On a sub-3nm NVCell standard-cell dataset, DRC-Coder achieves perfect $F1$ scores ($1.000$) across seven rules and reduces per-rule coding time to approximately $4$ minutes, vastly outperforming standard prompting. The approach demonstrates strong potential to accelerate technology migration, reduce engineering costs, and be extended to other DRC-related tasks and design domains.

Abstract

In the advanced technology nodes, the integrated design rule checker (DRC) is often utilized in place and route tools for fast optimization loops for power-performance-area. Implementing integrated DRC checkers to meet the standard of commercial DRC tools demands extensive human expertise to interpret foundry specifications, analyze layouts, and debug code iteratively. However, this labor-intensive process, requiring to be repeated by every update of technology nodes, prolongs the turnaround time of designing circuits. In this paper, we present DRC-Coder, a multi-agent framework with vision capabilities for automated DRC code generation. By incorporating vision language models and large language models (LLM), DRC-Coder can effectively process textual, visual, and layout information to perform rule interpretation and coding by two specialized LLMs. We also design an auto-evaluation function for LLMs to enable DRC code debugging. Experimental results show that targeting on a sub-3nm technology node for a state-of-the-art standard cell layout tool, DRC-Coder achieves perfect F1 score 1.000 in generating DRC codes for meeting the standard of a commercial DRC tool, highly outperforming standard prompting techniques (F1=0.631). DRC-Coder can generate code for each design rule within four minutes on average, which significantly accelerates technology advancement and reduces engineering costs.

Figures (11)

• Figure 1: DRC checker development process. The flow begins with the interpretation of foundry-provided description and a layout with its DRVs extracted from a commercial DRC tool report. Then, the flow comes to coding, alignment checking, and debugging. The proposed LLM-agent system automates this process, significantly reducing the development time compared to manual coding.
• Figure 2: Comparison of the response of two VLMs, GPT-4o and Phi-3, for (a) the design rule and (b) the layout. In layout image, yellow polygons are the metals in the M0 layer, black polygons are the DRV region marked by the commercial DRC tool, and black crosses are the corresponding DRV locations in grid-based coordinates.
• Figure 3: A grid-based DRC code for design rule M0.S.1.
• Figure 4: Conversion from DRVs in the commercial DRC tool report to grid-based DRVs. DRV locations in the commercial tool report are marked by black polygons, each defined by four points with x and y coordinates. Our grid-based approach identifies the layout components intersecting these polygons and represents DRVs using the grid coordinates of these components.
• Figure 5: Overview of DRC-Coder. Planner first interprets the input design rule by executing analysis tool functions. Programmer receives the rule condition to generate code. Finally, DRC code evaluation is executed to provide code performance feedback. Planner receives the feedback to perform re-reasoning, and Programmer performs debugging until generating the correct code.