BinSparX: Sparsified Binary Neural Networks for Reduced Hardware Non-Idealities in Xbar Arrays

TL;DR

The paper addresses the heightened sensitivity of CiM-BNNs to Xbar non-idealities in scaled hardware and introduces BinSparX, a training-free method that reduces the average partial-sums by statically sparsifying weights and dynamically sparsifying activations. By flipping weight columns and activation subvectors to minimize the number of ON bitcells, BinSparX lowers IR drops and mitigates inference errors, achieving up to near-ideal accuracy and $9$–$9.4 ext{0}$ energy savings, at the cost of moderate latency/area increases. Evaluations on 7nm 8T-SRAM and 1T-1ReRAM implementations of ResNet-18 and VGG-small show partial-sum reductions of $43.1$–$49.8 ext{0}$ and substantial accuracy gains across design points. The approach enables more reliable CiM-BNN deployment in scaled technologies with minimal hardware overhead, demonstrating the practical viability of non-ideality mitigation for edge AI.

Abstract

Compute-in-memory (CiM)-based binary neural network (CiM-BNN) accelerators marry the benefits of CiM and ultra-low precision quantization, making them highly suitable for edge computing. However, CiM-enabled crossbar (Xbar) arrays are plagued with hardware non-idealities like parasitic resistances and device non-linearities that impair inference accuracy, especially in scaled technologies. In this work, we first analyze the impact of Xbar non-idealities on the inference accuracy of various CiM-BNNs, establishing that the unique properties of CiM-BNNs make them more prone to hardware non-idealities compared to higher precision deep neural networks (DNNs). To address this issue, we propose BinSparX, a training-free technique that mitigates non-idealities in CiM-BNNs. BinSparX utilizes the distinct attributes of BNNs to reduce the average current generated during the CiM operations in Xbar arrays. This is achieved by statically and dynamically sparsifying the BNN weights and activations, respectively (which, in the context of BNNs, is defined as reducing the number of +1 weights and activations). This minimizes the IR drops across the parasitic resistances, drastically mitigating their impact on inference accuracy. To evaluate our technique, we conduct experiments on ResNet-18 and VGG-small CiM-BNNs designed at the 7nm technology node using 8T-SRAM and 1T-1ReRAM. Our results show that BinSparX is highly effective in alleviating the impact of non-idealities, recouping the inference accuracy to near-ideal (software) levels in some cases and providing accuracy boost of up to 77.25%. These benefits are accompanied by energy reduction, albeit at the cost of mild latency/area increase.

Figures (5)

• Figure 1: Histograms showing the frequency of ideal partial-sums in a (a) ResNet-18 BNN and (b) ResNet-18 with 4-bit weights and activations. The Xbar array size is 64x64. We observe that BNN produces larger partial-sums than the 4-bit DNN.
• Figure 2: (a) Xbar array column with non-idealities. (b-c) schematics and layout of 8T-SRAM and 1T-1ReRAM bitcells. (d) average current deviation (normalized to current quantum between adjacent ADC levels) versus partial-sum. The inset shows the range of current deviations for each partial sum corresponding to different input-weight combinations. Current deviation increases superlinearly with rising partial-sum.
• Figure 3: (a) Static weight sparsification being applied on a BNN weight column. (b) Hardware implementation of BinSparX.
• Figure 4: Average partial-sum reduction using BinSparX.
• Figure 5: Non-ideal inference accuracy for ResNet-18 and VGG-small CiM-BNNs across various hardware design points. Baseline CiM-BNN accuracy is severely degraded due to Xbar non-idealities, due to the large partial-sums. BinSparX is able to significantly improve accuracy, even bringing to near-ideal values for some cases. M3, M4 and M6 refer to the BL/SL routing metal layers, and 1 $\mu$A and 2 $\mu$A refer to the ON currents of the bit-cell. The 1T-ReRAM HRS current is $\sim$ 0.1 $\mu$A. We modulate the gap length in 1T-1ReRAM and the terminal voltages in 8T-SRAM to achieve the two different on-currents.