Integrating programmable plasticity in experiment descriptions for analog neuromorphic hardware

TL;DR

This work tackles the computational bottleneck of simulating plasticity in spiking neural networks by integrating programmable plasticity directly into the BrainScaleS-2 analog neuromorphic platform. It introduces a unified, PyNN-based experiment description framework that couples network topology, plasticity rules, and run-time protocols, with code generation enabling embedded processors to execute plasticity kernels in sync with the analog core. The approach provides an execution model, data flow, user interface, and evaluation showing scalable online plasticity through EDF scheduling, observable recording, and template-driven code generation. The result is a scalable, flexible pathway for real-time, hardware-accelerated plasticity experiments with quantified performance metrics and clear avenues for extension toward domain-specific languages and gradient-based training integrations.

Abstract

The study of plasticity in spiking neural networks is an active area of research. However, simulations that involve complex plasticity rules, dense connectivity/high synapse counts, complex neuron morphologies, or extended simulation times can be computationally demanding. The BrainScaleS-2 neuromorphic architecture has been designed to address this challenge by supporting "hybrid" plasticity, which combines the concepts of programmability and inherently parallel emulation. In particular, observables that are expensive in numerical simulation, such as per-synapse correlation measurements, are implemented directly in the synapse circuits. The evaluation of the observables, the decision to perform an update, and the magnitude of an update, are all conducted in a conventional program that runs simultaneously with the analog neural network. Consequently, these systems can offer a scalable and flexible solution in such cases. While previous work on the platform has already reported on the use of different kinds of plasticity, the descriptions for the spiking neural network experiment topology and protocol, and the plasticity algorithm have not been connected. In this work, we introduce an integrated framework for describing spiking neural network experiments and plasticity rules in a unified high-level experiment description language for the BrainScaleS-2 platform and demonstrate its use.

Figures (4)

• Figure 1: A photo of the chip with its schematic on top. One embedded processor per chip half accesses on-chip observables, such as synapse-local pre-/post-timed spike correlation information, mean neuronal activities, or firing rates, and modifies neuron and synapse parameterization (e.g., weights), and topology (e.g., to implement structural plasticity) defined by a plasticity algorithm.
• Figure 2: Scheduling of plasticity rules on the embedded processors. Different colors represent different plasticity rules. The program loops and fetches new events marking plasticity rules to be executed. It then checks whether the earliest event deadline has passed and issues the execution of the corresponding plasticity rule. The arrows represent the latency incurred between the event's deadline and the beginning of the execution of the associated rule. Events, for which the deadline passes during another execution are skipped (dashed event), except for the latest one, for which execution is additionally delayed by the amount of time passed in the execution of the current rule.
• Figure 3: Execution model for experiments on . The developed support for plasticity on the embedded processors is depicted in red, the previously implemented execution model including the host computer, , and neural network core on is depicted in gray. Playback programs for the for static configuration of the system and subsequent neural network time evolution are generated on the host computer. Execution on the is synchronized with the neural network core time evolution, e.g., by injecting external spike events. After execution, the responses from the system are read out to the host computer, post-processed, and provided to the user in PyNN. For plasticity, the embedded processors are provided with their program during the static configuration phase of the experiment. Concurrent with the time-continuous evolution of the analog neural network core, it accesses observables, updates network parameters and stores to-be-recorded observables. The scheduling of the plasticity rules on the embedded processors is time-synchronized at the beginning of the real-time section of the experiment by the . After completion of the concurrent real-time experiment execution, the recorded observable data and other responses are read out and made available to the user after post-processing.
• Figure 4: Evaluation of an exemplary homeostatic plasticity rule. A Poisson source of 120k (hardware time domain) projects via plastic synapses onto a variable number of target neurons, see (A). (B) shows the duration of compilation and code generation for the programs executed on the embedded processors. (C) shows the firing rate of the neurons (for 512 target neurons). The homeostatic plasticity is successful in converging the neurons' firing rate to the target firing rate of 6k (depicted in blue). Firing rates are extracted from the recorded spike trains by counting in bins of 50. Due to the source being Poisson, no perfect convergence to the target firing rate is expected. (D) shows the evolution of the synaptic weights. (E) shows the difference of the actual rule execution times to the expected/scheduled execution times. Due to using the earliest-deadline-first scheduler for rule execution, a constant positive shift of the actual to the expected execution time is visible. The occurrence of the higher difference is due to the instruction caches of the embedded processors being cold at the first rule execution. (F) shows the rule execution duration per plastic synapse in dependence of the number of target neurons. Here, the usage of the embedded processors unit shows runtime performance advantages for a higher number of target neurons. Between 512.0 and 256.0 target neurons a factor of two in runtime per plastic synapse is achieved due to both embedded processors executing the rule for their hemisphere in parallel for 512.0 target neurons, while for 256.0 only one processor is active.