Demonstrating the Advantages of Analog Wafer-Scale Neuromorphic Hardware

TL;DR

This work addresses the challenge of resource-intensive large-scale spiking-network simulations by showcasing BrainScaleS-1, a wafer-scale analog neuromorphic accelerator that provides continuous-time emulation with a speedup of about $10^4$× and energy benefits. By adapting two biologically inspired networks—the balanced random network and the cortical microcircuit—to hardware constraints, mapping them onto BrainScaleS-1, and comparing emulation against conventional simulators, the authors demonstrate hardware’s unique advantages in long-duration and iterative experiments. Key contributions include a detailed adaptation strategy (downscaling with preserved connectivity, conductance-based synapses, and calibrated parameter variations), empirical emulation results highlighting hardware limits and capabilities (e.g., mean firing rates up to $\sim$250 Hz, readout limitations per ASIC, and long-time evolution feasibility), and a practical co-execution workflow with PyNN/EBRAINS that enables remote, reproducible experiments. The findings suggest that wafer-scale analog neuromorphic hardware can meaningfully augment traditional simulations, particularly for extended or repetitive explorations, and point toward future improvements via smaller-node CMOS histories and expanded hardware flexibility.

Abstract

As numerical simulations grow in size and complexity, they become increasingly resource-intensive in terms of time and energy. While specialized hardware accelerators often provide order-of-magnitude gains and are state of the art in other scientific fields, their availability and applicability in computational neuroscience is still limited. In this field, neuromorphic accelerators, particularly mixed-signal architectures like the BrainScaleS systems, offer the most significant performance benefits. These systems maintain a constant, accelerated emulation speed independent of network model and size. This is especially beneficial when traditional simulators reach their limits, such as when modeling complex neuron dynamics, incorporating plasticity mechanisms, or running long or repetitive experiments. However, the analog nature of these systems introduces new challenges. In this paper we demonstrate the capabilities and advantages of the BrainScaleS-1 system and how it can be used in combination with conventional software simulations. We report the emulation time and energy consumption for two biologically inspired networks adapted to the neuromorphic hardware substrate: a balanced random network based on Brunel and the cortical microcircuit from Potjans and Diesmann.

Figures (3)

• Figure 1: A: Photograph of a fully assembled system. B: Close up of a wafer positioned at the center of the system shown in A. Wafer-scale integration is achieved through a redistribution layer applied atop the wafer. C: Visualization of the adapted cortical microcircuit mapped to a wafer. Each on the wafer is depicted as a rectangle with a white triangle at the bottom. The neuron placement is represented by the use of blue coloration, with darker shades indicating higher neuron counts. Connections are visualized as colored lines routed along the edges of the . The positions of different model populations (see E) on the wafer are highlighted with distinct colored borders. Due to design constraints, not all at the wafer's edge, as shown in B, are available for mapping. D: Connectivity of the balanced random network model. E: Structure of the cortical microcircuit model. Only connections with probabilities greater than 0.04 are displayed.
• Figure 2: Mean firing rate of neurons in the balanced random network model, emulated on (left) and simulated in NEST (right). Firing rates are reported across various relative inhibitory weights and external input spike rates. For firing rates exceeding 30Hz, saturation effects on the hardware introduce deviations in network behavior.
• Figure 3: Firing rate distribution of neurons across the eight populations within the cortical microcircuit, emulated on and simulated in NEST. Results are extracted from a 9s interval of biological time, starting 1s after the experiment onset. Furthermore, the emulation is reevaluated after the network has evolved over a 1.0-year period of biological time on the neuromorphic hardware.