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PrefixLLM: LLM-aided Prefix Circuit Design

Weihua Xiao, Venkata Sai Charan Putrevu, Raghu Vamshi Hemadri, Siddharth Garg, Ramesh Karri

TL;DR

The paper addresses the carry-generation bottleneck in wide-adders by proposing PrefixLLM, a framework that repurposes large language models to synthesize optimized prefix circuits. It introduces Structured Prefix Circuit Representation (SPCR), a text-based encoding of circuit nodes, connectivity, and bit ranges, and uses an iterative SPCR generation loop to ensure validity. Building on SPCR, PrefixLLM employs a design space exploration (DSE) loop with a sorted pool of prior designs and a Delay-SPCR variant to guide the search toward lower area and maintained or reduced delay. Empirical results show that PrefixLLM achieves up to 3.70% area reduction under the same delay for 16-bit circuits and demonstrates practical hardware viability via Tiny Tapeout, indicating that LLM-based synthesis can effectively contribute to arithmetic circuit design and optimization.

Abstract

Prefix circuits are fundamental components in digital adders, widely used in digital systems due to their efficiency in calculating carry signals. Synthesizing prefix circuits with minimized area and delay is crucial for enhancing the performance of modern computing systems. Recently, large language models (LLMs) have demonstrated a surprising ability to perform text generation tasks. We propose PrefixLLM, that leverages LLMs for prefix circuit synthesis. PrefixLLM transforms the prefix circuit synthesis task into a structured text generation problem, termed the Structured Prefix Circuit Representation (SPCR), and introduces an iterative framework to automatically and accurately generate valid SPCRs. We further present a design space exploration (DSE) framework that uses LLMs to iteratively search for area and delay optimized prefix circuits. Compared to state-of-the-art, PrefixLLM can reduce the area by 3.70% under the same delay constraint. This work highlights the use of LLMs in the synthesis of arithmetic circuits, which can be transformed into the structured text generation.

PrefixLLM: LLM-aided Prefix Circuit Design

TL;DR

The paper addresses the carry-generation bottleneck in wide-adders by proposing PrefixLLM, a framework that repurposes large language models to synthesize optimized prefix circuits. It introduces Structured Prefix Circuit Representation (SPCR), a text-based encoding of circuit nodes, connectivity, and bit ranges, and uses an iterative SPCR generation loop to ensure validity. Building on SPCR, PrefixLLM employs a design space exploration (DSE) loop with a sorted pool of prior designs and a Delay-SPCR variant to guide the search toward lower area and maintained or reduced delay. Empirical results show that PrefixLLM achieves up to 3.70% area reduction under the same delay for 16-bit circuits and demonstrates practical hardware viability via Tiny Tapeout, indicating that LLM-based synthesis can effectively contribute to arithmetic circuit design and optimization.

Abstract

Prefix circuits are fundamental components in digital adders, widely used in digital systems due to their efficiency in calculating carry signals. Synthesizing prefix circuits with minimized area and delay is crucial for enhancing the performance of modern computing systems. Recently, large language models (LLMs) have demonstrated a surprising ability to perform text generation tasks. We propose PrefixLLM, that leverages LLMs for prefix circuit synthesis. PrefixLLM transforms the prefix circuit synthesis task into a structured text generation problem, termed the Structured Prefix Circuit Representation (SPCR), and introduces an iterative framework to automatically and accurately generate valid SPCRs. We further present a design space exploration (DSE) framework that uses LLMs to iteratively search for area and delay optimized prefix circuits. Compared to state-of-the-art, PrefixLLM can reduce the area by 3.70% under the same delay constraint. This work highlights the use of LLMs in the synthesis of arithmetic circuits, which can be transformed into the structured text generation.

Paper Structure

This paper contains 12 sections, 4 equations, 9 figures, 1 table.

Table of Contents

  1. Introduction
  2. Preliminaries
  3. Prefix circuit
  4. LLM for Structured Text Generation
  5. LLM-aided Prefix Circuit Design
  6. LLM-aided Valid Prefix Circuit Synthesis
  7. LLM-aided Design Space Exploration of Prefix Circuits
  8. Experimental Results
  9. Experimental Setup
  10. Comparison of Synthesized Prefix Circuits
  11. Chip Tapeout
  12. Conclusion

Figures (9)

  • Figure 1: A $4$-bit valid prefix circuit with $4$ input nodes (nodes $0$-$3$) and $4$ valid prefix nodes (nodes $4$-$7$). Node $8$ is an example invalid prefix node.
  • Figure 2: (a) An example 4-bit valid prefix circuit with 4 input nodes and 5 prefix nodes; (b) the corresponding SPCR.
  • Figure 3: Iterative framework for prefix circuit synthesis.
  • Figure 4: SPCR Prompt: the two orange frames have to be changed according to the current partial prefix circuit, and the remaining parts are fixed.
  • Figure 5: Iterative DSE framework for optimizing prefix circuits.
  • ...and 4 more figures

Theorems & Definitions (1)

  • Definition 1