ML-based AIG Timing Prediction to Enhance Logic Optimization

TL;DR

The paper tackles the mismatch between proxy metrics and post-mapping PPA in logic optimization of AIGs. It proposes an ML-based timing predictor trained on AIG features to estimate post-mapping delay, enabling a timing-aware SA optimization flow that avoids repeated mapping and STA. Empirical results show the predictor achieves an average absolute error of $4.03\%$ and that the ML-based flow delivers similar design quality to a ground-truth flow while reducing runtime by up to $80\%$ (and up to $88.79\%$ on some designs). This approach scales to large designs by replacing expensive mapping steps with fast ML inference without sacrificing PPA, advancing practical logic synthesis.

Abstract

As circuit designs become more intricate, obtaining accurate performance estimation in early stages, for effective design space exploration, becomes more time-consuming. Traditional logic optimization approaches often rely on proxy metrics to approximate post-mapping performance and area. However, these proxies do not always correlate well with actual post-mapping delay and area, resulting in suboptimal designs. To address this issue, we explore a ground-truth-based optimization flow that directly incorporates the exact post-mapping delay and area during optimization. While this approach improves design quality, it also significantly increases computational costs, particularly for large-scale designs. To overcome the runtime challenge, we apply machine learning models to predict post-mapping delay and area using the features extracted from AIGs. Our experimental results show that the model has high prediction accuracy with good generalization to unseen designs. Furthermore, the ML-enhanced logic optimization flow significantly reduces runtime while maintaining comparable performance and area outcomes.

Figures (5)

• Figure 1: Scatter plot: post-mapping circuit delay vs. the number of AIG levels.
• Figure 2: Runtime comparison for one iteration in the original logic optimization flow and the ground-truth-based logic optimization flow. The x-axis shows the name of each designs, with the number of its AIG nodes in parentheses.
• Figure 3: Three flows for AIG optimization.
• Figure 4: Feature extraction in an example AIG. (a) The maximum depth is annotated for each PO. (b) The fanout of each node is annotated as the weight and the updated maximum depth is annotated for each PO. (c) The binary-encoded fanout of each node is annotated as the weight and the updated maximum depth is annotated for each PO. (d) The subgraph of PO1 is highlighed in blue, and the number of paths is annotated for each PO.
• Figure 5: A comparison of the Pareto-optimal fronts for the delay and area of a test design from the baseline, ground-truth-based, and ML-based flows.