Logo
ScienceStack
Table of Contents
Fetching ...
Sign In

High-Quality Iterative Logic Compiler for In-Memory SIMD Computation with Tight Coupling of Synthesis and Scheduling

Xingyue Qian, Chenyang Lv, Zhezhi He, Weikang Qian

TL;DR

The paper tackles the challenge of generating energy‑efficient instruction sequences for SIMD IMC by proposing an iterative, tightly coupled logic compiler that blends synthesis and scheduling. It introduces a Pareto‑front driven flow over netlist size and memory footprint, augmented by critical sub‑netlist extraction and MF‑oriented resubstitution to iteratively improve designs without full re‑scheduling. Across EPFL benchmarks on XMG‑GPPIC hardware, the approach achieves about an 18% average reduction in energy‑delay product compared with the state of the art and demonstrates substantial gains on large benchmarks with multi‑array execution. Overall, the work shows that targeting Pareto‑optimal tradeoffs and performing targeted, scheduling‑aware optimizations can yield higher‑quality, more efficient IMC designs suitable for high‑throughput SIMD computation.

Abstract

In-memory computing (IMC) with single instruction multiple data (SIMD) setup enables memory to perform operations on the stored data in parallel to achieve high throughput and energy saving. To instruct a SIMD IMC hardware to compute a function, a logic compiler is needed that involves two steps: logic synthesis and scheduling. Logic synthesis transforms the function into a netlist of supported operations. Scheduling determines the execution sequence and memory location of the operations and outputs the instruction sequence given to the hardware. In this work, we propose an iterative logic compiler with tight coupling of synthesis and scheduling to find high-quality instruction sequences. It is based on improving the critical sub-netlist identified by our algorithm and performing problem-specific resubstitution. The experimental results show that our compiler can obtain better instruction sequences with energy-delay products reduced by 18.0% on average compared to the best state-of-the-art method.

High-Quality Iterative Logic Compiler for In-Memory SIMD Computation with Tight Coupling of Synthesis and Scheduling

TL;DR

The paper tackles the challenge of generating energy‑efficient instruction sequences for SIMD IMC by proposing an iterative, tightly coupled logic compiler that blends synthesis and scheduling. It introduces a Pareto‑front driven flow over netlist size and memory footprint, augmented by critical sub‑netlist extraction and MF‑oriented resubstitution to iteratively improve designs without full re‑scheduling. Across EPFL benchmarks on XMG‑GPPIC hardware, the approach achieves about an 18% average reduction in energy‑delay product compared with the state of the art and demonstrates substantial gains on large benchmarks with multi‑array execution. Overall, the work shows that targeting Pareto‑optimal tradeoffs and performing targeted, scheduling‑aware optimizations can yield higher‑quality, more efficient IMC designs suitable for high‑throughput SIMD computation.

Abstract

In-memory computing (IMC) with single instruction multiple data (SIMD) setup enables memory to perform operations on the stored data in parallel to achieve high throughput and energy saving. To instruct a SIMD IMC hardware to compute a function, a logic compiler is needed that involves two steps: logic synthesis and scheduling. Logic synthesis transforms the function into a netlist of supported operations. Scheduling determines the execution sequence and memory location of the operations and outputs the instruction sequence given to the hardware. In this work, we propose an iterative logic compiler with tight coupling of synthesis and scheduling to find high-quality instruction sequences. It is based on improving the critical sub-netlist identified by our algorithm and performing problem-specific resubstitution. The experimental results show that our compiler can obtain better instruction sequences with energy-delay products reduced by 18.0% on average compared to the best state-of-the-art method.

Paper Structure

This paper contains 18 sections, 1 equation, 7 figures, 2 tables, 1 algorithm.

Table of Contents

  1. Introduction
  2. Preliminaries
  3. Netlist Representation and Basic Scheduling Rules
  4. Resubstitution
  5. Motivation
  6. Method
  7. Critical Sub-netlist Optimization
  8. Critical Sub-netlist Extraction
  9. Sub-netlist Optimization
  10. Sub-netlist Scheduling
  11. MF-Oriented Resubstitution
  12. Case 1
  13. Case 2
  14. Experimental Results
  15. Small Benchmarks Using A Single Array
  16. ...and 3 more sections

Figures (7)

  • Figure 1: (a) The flow of a SIMD IMC logic compiler; (b) a netlist example. Note that some operations in the figure only have two fan-ins, because we omit the constant 0 for simplicity; (c) a scheduling result example.
  • Figure 2: Design space of x2 function on MF-size plane.
  • Figure 3: The flow of our iterative logic compiler.
  • Figure 4: (a) Memory usage and critical sub-netlist of log2 benchmark; (b) an example critical sub-netlist.
  • Figure 5: The two cases of MF-oriented resubstitution: (a) case 1; (b) case 2.
  • ...and 2 more figures

Theorems & Definitions (6)

  • Example 1
  • Example 2
  • Example 3
  • Example 4
  • Example 5
  • Example 6