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Agentic-HLS: An agentic reasoning based high-level synthesis system using large language models (AI for EDA workshop 2024)

Ali Emre Oztas, Mahdi Jelodari

TL;DR

Agentic-HLS targets predicting HLS design validity, latency, and resource utilizations by combining HARP-based graph embeddings, source-code sequence analysis, and agentic LLM reasoning. The approach uses fine-tuned HARP and GPT-4o guided reasoning with a predictor/criticiser loop to iteratively refine predictions. Empirical results show that while GPT-4o alone is weaker, fine-tuned HARP and the Agentic-HLS pipeline offer substantial improvements in RMSE, with Agentic-HLS achieving competitive performance through multi-cycle reasoning. The work contributes prompts and an HLS benchmarking task for LLMs, highlighting the potential of agentive AI to accelerate hardware design exploration.

Abstract

Our aim for the ML Contest for Chip Design with HLS 2024 was to predict the validity, running latency in the form of cycle counts, utilization rate of BRAM (util-BRAM), utilization rate of lookup tables (uti-LUT), utilization rate of flip flops (util-FF), and the utilization rate of digital signal processors (util-DSP). We used Chain-of-thought techniques with large language models to perform classification and regression tasks. Our prediction is that with larger models reasoning was much improved. We release our prompts and propose a HLS benchmarking task for LLMs.

Agentic-HLS: An agentic reasoning based high-level synthesis system using large language models (AI for EDA workshop 2024)

TL;DR

Agentic-HLS targets predicting HLS design validity, latency, and resource utilizations by combining HARP-based graph embeddings, source-code sequence analysis, and agentic LLM reasoning. The approach uses fine-tuned HARP and GPT-4o guided reasoning with a predictor/criticiser loop to iteratively refine predictions. Empirical results show that while GPT-4o alone is weaker, fine-tuned HARP and the Agentic-HLS pipeline offer substantial improvements in RMSE, with Agentic-HLS achieving competitive performance through multi-cycle reasoning. The work contributes prompts and an HLS benchmarking task for LLMs, highlighting the potential of agentive AI to accelerate hardware design exploration.

Abstract

Our aim for the ML Contest for Chip Design with HLS 2024 was to predict the validity, running latency in the form of cycle counts, utilization rate of BRAM (util-BRAM), utilization rate of lookup tables (uti-LUT), utilization rate of flip flops (util-FF), and the utilization rate of digital signal processors (util-DSP). We used Chain-of-thought techniques with large language models to perform classification and regression tasks. Our prediction is that with larger models reasoning was much improved. We release our prompts and propose a HLS benchmarking task for LLMs.

Paper Structure

This paper contains 9 sections, 3 figures, 1 table.

Table of Contents

  1. Introduction
  2. Methodology
  3. Fine-tuning HARP
  4. Source Code Analysis
  5. Reasoning
  6. Agentic Evaluation
  7. Results
  8. Discussion
  9. Acknowledgment

Figures (3)

  • Figure 1: Agentic-HLS system architecture, a LLM+GNN system that uses agentic reasoning to iteratively review its output and refine its predictions.
  • Figure 2: High level reasoning of the target kernel (left) and pragma impact on the control and data flow of the kernel generated by GPT4o (right).
  • Figure 3: t-SNE representations of graph embeddings for the spmv-ellpack kernel with different Pragma values: (a) PARALLEL, (b) PIPE, (c) TILE.