HT-HEDL: High-Throughput Hypothesis Evaluation in Description Logic

TL;DR

HT-HEDL tackles the scalability bottleneck of DL-based ILP by leveraging a heterogeneous compute platform to accelerate hypothesis evaluation at three levels: individual DL operators, single-hypothesis evaluation, and batch hypothesis throughput. It introduces a matrix-based, SIMD-optimized knowledge representation and bespoke CPU/GPU implementations for conjunction, disjunction, role restrictions, and concrete role restrictions, plus a static multi-device scheduling strategy that uses a dummy probe to estimate device capabilities. Empirical results show dramatic speedups, including up to $\\sim85$-fold CPU vectorization, up to $\\sim38$-fold GPU acceleration for single hypotheses, and up to $\\sim44$-fold throughput gains when using two GPUs plus CPU for batches of hypotheses. The approach reduces ILP learning times and demonstrates the practical viability of HT-HEDL for large, DL-based ILP workloads, with prospects for further hardware integration and richer DL features.

Abstract

We present High-Throughput Hypothesis Evaluation in Description Logic (HT-HEDL). HT-HEDL is a high-performance hypothesis evaluation engine that accelerates hypothesis evaluation computations for inductive logic programming (ILP) learners using description logic (DL) for their knowledge representation; in particular, HT-HEDL targets accelerating computations for the $\mathcal{ALCQI}^{\mathcal{(D)}}$ DL language. HT-HEDL aggregates the computing power of multi-core CPUs with multi-GPUs to improve hypothesis computations at two levels: 1) the evaluation of a single hypothesis and 2) the evaluation of multiple hypotheses (i.e., batch of hypotheses). In the first level, HT-HEDL uses a single GPU or a vectorized multi-threaded CPU to evaluate a single hypothesis. In vectorized multi-threaded CPU evaluation, classical (scalar) CPU multi-threading is combined with CPU's extended vector instructions set to extract more CPU-based performance. The experimental results revealed that HT-HEDL increased performance using CPU-based evaluation (on a single hypothesis): from 20.4 folds using classical multi-threading to $\sim85$ folds using vectorized multi-threading. In the GPU-based evaluation, HT-HEDL achieved speedups of up to $\sim38$ folds for single hypothesis evaluation using a single GPU. To accelerate the evaluation of multiple hypotheses, HT-HEDL combines, in parallel, GPUs with multi-core CPUs to increase evaluation throughput (number of evaluated hypotheses per second). The experimental results revealed that HT-HEDL increased evaluation throughput by up to 29.3 folds using two GPUs and up to $\sim44$ folds using two GPUs combined with a CPU's vectorized multi-threaded evaluation.

Figures (10)

• Figure 1: HT-HEDL knowledge representation.
• Figure 2: DL hypothesis representation in HT-HEDL.
• Figure 3: Example of HT-HEDL's multi-device scheduling using four GPUs and one multi-core CPU.
• Figure 4: Visualization of HT-HEDL's multi-device evaluation of 1000 hypotheses using the same four GPUs and one multi-core CPU.
• Figure 5: Evaluation of conjunction operator.