Controller-decoder system requirements derived by implementing Shor's algorithm with surface code

TL;DR

This work tackles the challenge of running non-Clifford quantum circuits under surface-code QEC by presenting an end-to-end analysis of a controller–decoder system (CDS) using Shor’s factorization of 21 as a concrete benchmark. It maps the logical circuit to a surface-code, then to a physical-level circuit, and performs end-to-end simulations to derive concrete CDS requirements, including latency, throughput, and the resources needed for decoding. The results show that with realistic superconducting hardware assumptions (approximately $P_{ ext{phys}} \, ext{about}\, 0.1\%$ and code distance $d\ge 5$), around $10^3$ physical qubits suffice to execute roughly $15$ non-Clifford gates while keeping circuit error below an actionable threshold ($\varepsilon_{\text circ} \lesssim 8.6\%$), though magic-state initialization dominates the error budget. The findings establish practical design targets for CDS in near- and medium-term non-Clifford QEC circuits and outline architectural and algorithmic directions for scaling toward fault-tolerant quantum computation.

Abstract

Quantum Error Correction (QEC) is regarded as the most promising path to quantum advantage. The success of QEC relies on achieving quantum gate fidelities below the error threshold of the QEC code, while accurately decoding errors through classical processing of the QEC stabilizer measurements. In this paper, we uncover the critical system-level requirements from a controller-decoder system (CDS) necessary to successfully execute the next milestone in QEC: a non-Clifford circuit. Using a representative non-Clifford circuit, of Shor factorization algorithm for the number 21, we convert the logical-level circuit to a QEC surface code circuit and finally to the physical level circuit. By taking into account realistic implementation aspects using typical superconducting qubit processor parameters, we reveal a broad range of core requirements from any CDS aimed at performing error corrected quantum computation. Our findings indicate that the controller-decoder closed-loop latency must remain within tens of microseconds, achievable by distributing decoding data into several decoders while ensuring fast communication between decoders and with the controller. By extending existing simulation techniques, we simulate the complete fault-tolerant factorization circuit at the physical level, demonstrating that near-term hardware performance in the scale of 0.1% physical error rates and 1000 qubits, are sufficient for a successful circuit execution. Overall, the requirements outlined here set the stage for near- and medium-term experimental realizations of non-Clifford QEC circuits.

Figures (8)

• Figure 1: Controller-decoder system (CDS) for executing non-Clifford QEC circuits. (a) The examined logical circuit which factorizes the number $21$. (b) A distance-3 surface-code layout. Data qubits (black) store the logical information; ancilla qubits (blue, pink) perform stabilizer measurements. (c) Control and decoding stack: a high-performance computer (HPC) compiles the logical circuit and chosen QEC code into real-time instructions for the controller-decoder system (CDS, dashed red), comprising the quantum controller and low-latency HPC nodes implementing the decoder. During execution, the controller drives the QPU, streams stabilizer outcomes (syndromes) to the decoder, and applies feed-forward updates to subsequent gates as a result of real-time decoding. The resulting real-time data flow and processing set explicit requirements on CDS latency, throughput, resources, and structure, needed for surface-code-protected non-Clifford circuits.
• Figure 2: Surface-code quantum computation. (a) Fault-tolerant (FT) two-surface gates are performed via lattice surgery, i.e., measurements the parity in the $Z/X$ bases between multiple surfaces. Shown is an $XX$ parity measurement using a line of ancillary qubits which are initialized, take part in $d$ stabilizer rounds (depth-8 circuit) on the merged surface, and then measured to terminate the surgery. (b) Logical surface-level building blocks: FT initializations/measurements along logical Pauli axes and lattice surgeries, and a non-Clifford gate implemented by a magic-state preparation with decoder-dependent feed-forward. We chose a $T=\mathrm{diag}(1,e^{i\pi/4})$ gate, using a $\ket{T}=\ket{0}+e^{i\pi/4}\ket{1}$ state that can be prepared A non-FT within $d$ rounds or with higher fidelity using distillation or cultivation at larger space--time cost. In this $T$-gate implementation, the feed-forward (e.g., an $S$-gate correction) must be applied before the next non-commuting gate. In all types of surface codes gates, measuring an ancillary surface modifies a computational qubit Pauli frame (dashed). (c) Surface-level circuit example: a logical CNOT (cyan) followed by a $T$ gate (yellow) using five surfaces. Each timestamp equals $d$ stabilizer rounds. In this example, all surfaces are active at timestamps 3 and 4. The $q_2$ and $\ket{S}$ surfaces continue to idle (via stabilizer rounds) before their decoding-dependent surgery, until the controller knows the decoding outcome of the yellow $ZZ$ at 3.
• Figure 3: The surface-level factorization circuit. (a) Surface-code–compatible logical circuit derived from Fig. \ref{['fig:illustration']}a using the logical building-block gates of Fig. \ref{['fig:logical_to_surface']}b. (b) Surface-level implementation of the factorization circuit with 18 surfaces. The computational surfaces $q_1$–$q_5$ (colored) are continuously teleported to satisfy the logical gate implementations geometric constraints. Fault-tolerant (FT) gates are indicated in blue–purple, and magic-state (MS) initializations in green. Because each logical gate spans multiple surface-level timestamps, we parallelize their execution when possible. Insets show top views of timestamps 7 and 18, corresponding to parts of the gates highlighted in (a). Our manual layout could be further optimized for surface count, circuit depth, or feed-forward timestamps between the conditional gates and their control measurement. Feed-forward can be delayed when commuting with subsequent gates (timestamps 20–31 on $q_0$, surface $(2,2)$) or be delayed until an ancilla becomes available (timestamps 12–15 on $q_3$, surface $(1,1)$).
• Figure 4: Error estimation for the factorization circuit. (a) Single FT error example: logical error from idling for $d$ stabilizer rounds. (b) Error from a non-FT magic-state initialization using state injection. Increasing code distance does not suppress this contribution. (c) Estimated total error for the circuit, computed binomially as the probability of an odd number of flips across 14 nFT gates and 296 FT gates. Inset: total error versus distance $d$, saturating near $\sim5\%$. From this estimate, achieving a circuit error below 8.6%, as needed from our circuit (see Appendix \ref{['app:circuit']}) requires a physical error rate of $\approx0.1\%$ and $d\!\ge\!5$.
• Figure 5: Physical-level simulation results of the factorization circuit. (a) Simulated logical circuit mirroring Fig. 3(a), with $T$ gates replaced by $S$ gates implemented (marked in red). The simulated physical-level implementation omits feed-forward. (b) Logical error versus physical error, with and without post-selection (PS). Because of non-FT magic-state initializations, the gain at $d{=}7$ is negligible relative to $d{=}5$ for physical errors of $0.1\%$. Target logical error of $8.6\%$ is out of reach at $0.3\%$ physical error. Error bars indicate $99.9\%$ binomial confidence intervals. (c) Logical error versus code distance $d$, showing saturation with increasing $d$ due to dominance of magic-state initializations errors.