Fused-MemBrain: a spiking processor combining CMOS and self-assembled memristive networks

TL;DR

Fused-MemBrain proposes a CMOS-neuron layer interfaced with a self-assembled memristive plexus to realize a syncytial-like, high-density neuromorphic network. It argues that a memristive plexus can replace conventional synapses, enabling scalable, low-area connectivity while preserving rich dynamical behavior. The authors provide an open-source simulator incorporating a lif-LIF neuron model and a memristor dynamics with $dg/dt=(1-g)k_p(V)-g k_d(V)$, where $k_p(V)=k_{p0}e^{\eta_p|V|}$ and $k_d(V)=k_{d0}e^{\eta_d|V|}$, along with the conductance-current relation $I(t)=[gG_{\max}+(1-g)G_{\min}]V(t)$ and an attractor $\tilde{g}=\frac{k_p}{k_p+k_d}$. The work discusses reservoir-computing-like uses, pattern storage, higher-order interactions from the planar plexus, and practical embedding considerations, providing a path toward hardware realizations and further exploration of self-assembled materials in neuromorphic circuits.

Abstract

In an era characterized by the rapid growth of data processing, developing new and efficient data processing technologies has become a priority. We address this by proposing a novel type of neuromorphic technology we call Fused-MemBrain. Our proposal is inspired by Golgi's theory modeling the brain as a syncytial continuum, in contrast to Cajal's theory of neurons and synapses being discrete elements. While Cajal's theory has long been the dominant and experimentally validated view of the nervous system, recent discoveries showed that a species of marine invertebrate (ctenophore Mnemiopsis leidyi) may be better described by Golgi's theory. The core idea is to develop hardware that functions analogously to a syncytial network, exploiting self-assembled memristive systems and combining them with CMOS technologies, interfacing with the silicon back-end-of-line. In this way, a memristive self-assembled material can cheaply and efficiently replace the synaptic connections between CMOS neuron implementations in neuromorphic hardware, enhancing the capability of massively parallel computation. The fusion of CMOS circuits with a memristive ``plexus'' allows information transfer without requiring engineered synapses, which typically consume significant area. As the first step toward this ambitious goal, we present a simulation of a memristive network interfaced with spiking neural networks. Additionally, we describe the potential benefits of such a system, along with key technical aspects it should incorporate.

Figures (4)

• Figure 1: The proposed Fused-MemBrain processor.a) A schematic depiction of the proposed hardware. A CMOS layer contains all of the neuron circuitry and configuration. On top, a self-assembled memristive material is deposited. The interfacing of the two layers is facilitated by electrodes protruding from the uppermost layers of . b) an exemplary neuron circuit adapted from Chicca2014. The neuron integrates input currents from the plexus through one of its two electrodes (in electrode). Once the neuron's membrane voltage crosses its firing threshold, it generates and transmits a voltage pulse (spike). This pulse can be fed back into the plexus via another electrode (out electrode), stimulating recurrent network activity.
• Figure 2: CMOS neuron configuration.a) The spike-pulse shape is illustrated. b) Input nodes are located in the central region of the plexus delimited by the square perimeter. They inject the input data and drive the system out of equilibrium. They are disposed to reflect the 20 higher-intensity coarse-grained pixels of a zero-digit sample from the MNIST dataset.
• Figure 3: Signal propagation through the memristive plexus across space and time. A voltage pulse of magnitude 1.5 and width of 1 is applied through an input electrode at the bottom left corner of the plexus indicated by the red arrow. The signal propagates through the planar system of memristively-coupled neurons (depicted by the purple squares). The activation pulse is sufficient to initiate the neurons' self-sustained activity. Note how the conductance distribution (red edges) is shaped by the activity of the network, producing clusters in regions with a higher density of neurons. The size of the simulated system is 1025$\times$1025.
• Figure 4: Example network activity. a) The firing activity of the neurons. The top inset depicts the initial propagation of the activity, while the bottom inset depicts the activity at a later time. b) The self-sustained neural activity raises the average conductivity from the initial pristine value of the plexus. c) The average firing rate of the neurons in the network. d) The voltage that neuron 0 applies to the plexus. The neuron begins firing early as it is located close to the origin of the activation signal (bottom left corner of the plexus).