Optimising Iteration Scheduling for Full-State Vector Simulation of Quantum Circuits on FPGAs

TL;DR

A memory access pattern is presented to optimise the number of iterations that need to be scheduled to execute a quantum gate such that only the iterations which access the required pairs (determined according to the control qubits imposed on the gate) are scheduled.

Abstract

As the field of quantum computing grows, novel algorithms which take advantage of quantum phenomena need to be developed. As we are currently in the NISQ (noisy intermediate scale quantum) era, quantum algorithm researchers cannot reliably test their algorithms on real quantum hardware, which is still too limited. Instead, quantum computing simulators on classical computing systems are used. In the quantum circuit model, quantum bits (qubits) are operated on by quantum gates. A quantum circuit is a sequence of such quantum gates operating on some number of qubits. A quantum gate applied to a qubit can be controlled by other qubits in the circuit. This applies the gate only to the states which satisfy the required control qubit state. We particularly target FPGAs as our main simulation platform, as these offer potential energy savings when compared to running simulations on CPUs/GPUs. In this work, we present a memory access pattern to optimise the number of iterations that need to be scheduled to execute a quantum gate such that only the iterations which access the required pairs (determined according to the control qubits imposed on the gate) are scheduled. We show that this approach results in a significant reduction in the time required to simulate a gate for each added control qubit. We also show that this approach benefits the simulation time on FPGAs more than CPUs and GPUs and allows to outperform both CPU and GPU platforms in terms of energy efficiency, which is the main factor for scalability of the simulations.

Figures (10)

• Figure 1: Illustration of simple two-qubit quantum circuits.
• Figure 2: Memory access pattern example for 3-qubit full state vector simulation. The numbers on the state vector represent the index of the complex probability amplitude. The box in the bottom part of the figure shows how the amplitudes are accessed depending on different target qubits. Like-coloured boxes are accessed and computed on together.
• Figure 3: Full state vector gate simulation kernel pseudocode. $2^{n-1}$ iterations of this kernel are scheduled by default. It can be seen that the memory access depends on dynamic control flow based on the control qubits imposed on the quantum gate.
• Figure 4: Access patterns for controlled gate applications for a 3-qubit register. For demonstration, the boxes representing the amplitudes are rearranged such that required pairs are contiguous, in contrast to Figure \ref{['fig:qwm_memory_access']}. Crossed out pairs indicate skipped iterations due to the controls imposed on the gate. It can be observed that the pattern of control skips is the same when controls are arranged in ascending order, as shown.
• Figure 5: Implementation of the iterative formula for going from a reduced iteration index set to the global set in the OpenCL kernel. Example shown for up to 2 controls.