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High-Performance and Scalable Fault-Tolerant Quantum Computation with Lattice Surgery on a 2.5D Architecture

Yosuke Ueno, Taku Saito, Teruo Tanimoto, Yasunari Suzuki, Yutaka Tabuchi, Shuhei Tamate, Hiroshi Nakamura

TL;DR

The Bypass architecture is a 2.5-dimensional architecture consisting of dense and sparse qubit layers and successfully eliminates the bottleneck to achieve high-performance and scalable LS-based FTQC, and improves the fidelity of FTQC.

Abstract

Due to the high error rate of a qubit, detecting and correcting errors on it is essential for fault-tolerant quantum computing (FTQC). Among several FTQC techniques, lattice surgery (LS) using surface code (SC) is currently promising. To demonstrate practical quantum advantage as early as possible, it is indispensable to propose a high-performance and low-overhead FTQC architecture specialized for a given FTQC scheme based on detailed analysis. In this study, we first categorize the factors, or hazards, that degrade LS-based FTQC performance and propose a performance evaluation methodology to decompose the impact of each hazard, inspired by the CPI stack. We propose the Bypass architecture based on the bottleneck analysis using the proposed evaluation methodology. The proposed Bypass architecture is a 2.5-dimensional architecture consisting of dense and sparse qubit layers and successfully eliminates the bottleneck to achieve high-performance and scalable LS-based FTQC. We evaluate the proposed architecture with a circuit-level stabilizer simulator and a cycle-accurate LS simulator with practical quantum phase estimation problems. The results show that the Bypass architecture improves the fidelity of FTQC and achieves both a 1.73x speedup and a 17% reduction in classical/quantum hardware resources over a conventional 2D architecture.

High-Performance and Scalable Fault-Tolerant Quantum Computation with Lattice Surgery on a 2.5D Architecture

TL;DR

The Bypass architecture is a 2.5-dimensional architecture consisting of dense and sparse qubit layers and successfully eliminates the bottleneck to achieve high-performance and scalable LS-based FTQC, and improves the fidelity of FTQC.

Abstract

Due to the high error rate of a qubit, detecting and correcting errors on it is essential for fault-tolerant quantum computing (FTQC). Among several FTQC techniques, lattice surgery (LS) using surface code (SC) is currently promising. To demonstrate practical quantum advantage as early as possible, it is indispensable to propose a high-performance and low-overhead FTQC architecture specialized for a given FTQC scheme based on detailed analysis. In this study, we first categorize the factors, or hazards, that degrade LS-based FTQC performance and propose a performance evaluation methodology to decompose the impact of each hazard, inspired by the CPI stack. We propose the Bypass architecture based on the bottleneck analysis using the proposed evaluation methodology. The proposed Bypass architecture is a 2.5-dimensional architecture consisting of dense and sparse qubit layers and successfully eliminates the bottleneck to achieve high-performance and scalable LS-based FTQC. We evaluate the proposed architecture with a circuit-level stabilizer simulator and a cycle-accurate LS simulator with practical quantum phase estimation problems. The results show that the Bypass architecture improves the fidelity of FTQC and achieves both a 1.73x speedup and a 17% reduction in classical/quantum hardware resources over a conventional 2D architecture.

Paper Structure

This paper contains 33 sections, 1 theorem, 18 figures, 3 tables.

Table of Contents

  1. Introduction
  2. Background on LS-based FTQC
  3. Quantum error correction with SCs
  4. LS and gate teleportation with magic states
  5. Qubit plane for LS-based FTQC
  6. LS instruction set
  7. LS instruction scheduling and hazards
  8. LS instruction scheduling
  9. Hazards on LS-based FTQC
  10. Path conflict
  11. Shortage of magic states
  12. Decoding process
  13. Performance analytical methodology
  14. Bypass architecture with 2.5D qubit layout
  15. Overview
  16. ...and 18 more sections

Key Result

theorem 1

$R_{data}$ of any IO-capable arrangements is at most $50\%$.

Figures (18)

  • Figure 1: FTQC performance evaluation using CBPI stack for a QPE program. Section \ref{['subsec:setup_LS_simulation']} details the experimental setup.
  • Figure 2: Our research goal.
  • Figure 3: (a) Stabilizer-level picture of SC ($d=5$). (b) Merge operation for MEAS_ZZ instruction (Stabilizer-level view). (c) Cell- and stabilizer-level views of qubit plane during MEAS_XX instruction.
  • Figure 4: Procedure of each instruction in Table \ref{['tab:instruction_set']}.
  • Figure 5: (a) Path hazard caused by two LS operations. (b) Magic hazard. (c) A gate-teleportation circuit to perform $T$ gate with a magic state $\ket{M}$ and its error decoding scheme with Pauli frameknill2005quantum. (d) Decoding hazard.
  • ...and 13 more figures

Theorems & Definitions (1)

  • theorem 1