Logo
ScienceStack
Table of Contents
Fetching ...
Sign In

Mera: Memory Reduction and Acceleration for Quantum Circuit Simulation via Redundancy Exploration

Yuhong Song, Edwin Hsing-Mean Sha, Longshan Xu, Qingfeng Zhuge, Zili Shao

TL;DR

A multi-level optimization, namely Mera, is proposed by exploring memory and computation redundancy by designing a customized structure for significant memory saving as a regularity-oriented simulation for dense Hadamard gate simulation.

Abstract

With the development of quantum computing, quantum processor demonstrates the potential supremacy in specific applications, such as Grovers database search and popular quantum neural networks (QNNs). For better calibrating the quantum algorithms and machines, quantum circuit simulation on classical computers becomes crucial. However, as the number of quantum bits (qubits) increases, the memory requirement grows exponentially. In order to reduce memory usage and accelerate simulation, we propose a multi-level optimization, namely Mera, by exploring memory and computation redundancy. First, for a large number of sparse quantum gates, we propose two compressed structures for low-level full-state simulation. The corresponding gate operations are designed for practical implementations, which are relieved from the longtime compression and decompression. Second, for the dense Hadamard gate, which is definitely used to construct the superposition, we design a customized structure for significant memory saving as a regularity-oriented simulation. Meanwhile, an ondemand amplitude updating process is optimized for execution acceleration. Experiments show that our compressed structures increase the number of qubits from 17 to 35, and achieve up to 6.9 times acceleration for QNN.

Mera: Memory Reduction and Acceleration for Quantum Circuit Simulation via Redundancy Exploration

TL;DR

A multi-level optimization, namely Mera, is proposed by exploring memory and computation redundancy by designing a customized structure for significant memory saving as a regularity-oriented simulation for dense Hadamard gate simulation.

Abstract

With the development of quantum computing, quantum processor demonstrates the potential supremacy in specific applications, such as Grovers database search and popular quantum neural networks (QNNs). For better calibrating the quantum algorithms and machines, quantum circuit simulation on classical computers becomes crucial. However, as the number of quantum bits (qubits) increases, the memory requirement grows exponentially. In order to reduce memory usage and accelerate simulation, we propose a multi-level optimization, namely Mera, by exploring memory and computation redundancy. First, for a large number of sparse quantum gates, we propose two compressed structures for low-level full-state simulation. The corresponding gate operations are designed for practical implementations, which are relieved from the longtime compression and decompression. Second, for the dense Hadamard gate, which is definitely used to construct the superposition, we design a customized structure for significant memory saving as a regularity-oriented simulation. Meanwhile, an ondemand amplitude updating process is optimized for execution acceleration. Experiments show that our compressed structures increase the number of qubits from 17 to 35, and achieve up to 6.9 times acceleration for QNN.

Paper Structure

This paper contains 18 sections, 4 theorems, 15 equations, 9 figures, 4 tables, 1 algorithm.

Table of Contents

  1. Introduction
  2. Background, Related Works and Motivations
  3. Basics of quantum circuit simulation
  4. Related Works
  5. Motivations
  6. Design
  7. Low-level Simulation
  8. Compressed structures: DAX and DAS
  9. Corresponding MTP and MVM design of DAX and DAS
  10. Regularity-oriented Simulation
  11. RH structure
  12. MVM acceleration with RH
  13. Experimental Results
  14. Experimental Setup
  15. Evaluation for DAX and DAS structures
  16. ...and 3 more sections

Key Result

Theorem 1

Let $R(A)$ and $R(B)$ be the zero ratios of matrix $A$ and $B$. Thus, the sparsity of the $A$ and $B$ MTP result is

Figures (9)

  • Figure 1: Two compressed structures: (a) DAX and (b) DAS. Utilize Pauli-Y $\otimes$ Pauli-X gates as an example.
  • Figure 2: MTP computation of (a) DAX and (b) DAS structures. Utilize Pauli-Y $\otimes$ Pauli-X as an example.
  • Figure 3: The process of sign computation in matrix $H^{\otimes n}$ for a given index. Here, the number of qubits $n = 3$.
  • Figure 4: Three sign computation methods of $H^{\otimes n}$. (a) quarter-based method; (b) block-based method; (c) logarithm-based method. Here, the number of qubit $n$ = 5.
  • Figure 5: Maximum number of qubits and the memory improvement of DAX and DAS compared with original 'Matrix' structure.
  • ...and 4 more figures

Theorems & Definitions (6)

  • Theorem 1
  • Corollary 1
  • Theorem 2
  • Proof 1
  • Theorem 3
  • Proof 2