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Effective Analog ICs Floorplanning with Relational Graph Neural Networks and Reinforcement Learning

Davide Basso, Luca Bortolussi, Mirjana Videnovic-Misic, Husni Habal

TL;DR

This paper presents a novel automatic floorplanning algorithm based on reinforcement learning augmented by a relational graph convolutional neural network model for encoding circuit features and positional constraints that surpassed established floorplanning techniques in terms of speed, area and half-perimeter wire length.

Abstract

Analog integrated circuit (IC) floorplanning is typically a manual process with the placement of components (devices and modules) planned by a layout engineer. This process is further complicated by the interdependence of floorplanning and routing steps, numerous electric and layout-dependent constraints, as well as the high level of customization expected in analog design. This paper presents a novel automatic floorplanning algorithm based on reinforcement learning. It is augmented by a relational graph convolutional neural network model for encoding circuit features and positional constraints. The combination of these two machine learning methods enables knowledge transfer across different circuit designs with distinct topologies and constraints, increasing the \emph{generalization ability} of the solution. Applied to $6$ industrial circuits, our approach surpassed established floorplanning techniques in terms of speed, area and half-perimeter wire length. When integrated into a \emph{procedural generator} for layout completion, overall layout time was reduced by $67.3\%$ with a $8.3\%$ mean area reduction compared to manual layout.

Effective Analog ICs Floorplanning with Relational Graph Neural Networks and Reinforcement Learning

TL;DR

This paper presents a novel automatic floorplanning algorithm based on reinforcement learning augmented by a relational graph convolutional neural network model for encoding circuit features and positional constraints that surpassed established floorplanning techniques in terms of speed, area and half-perimeter wire length.

Abstract

Analog integrated circuit (IC) floorplanning is typically a manual process with the placement of components (devices and modules) planned by a layout engineer. This process is further complicated by the interdependence of floorplanning and routing steps, numerous electric and layout-dependent constraints, as well as the high level of customization expected in analog design. This paper presents a novel automatic floorplanning algorithm based on reinforcement learning. It is augmented by a relational graph convolutional neural network model for encoding circuit features and positional constraints. The combination of these two machine learning methods enables knowledge transfer across different circuit designs with distinct topologies and constraints, increasing the \emph{generalization ability} of the solution. Applied to industrial circuits, our approach surpassed established floorplanning techniques in terms of speed, area and half-perimeter wire length. When integrated into a \emph{procedural generator} for layout completion, overall layout time was reduced by with a mean area reduction compared to manual layout.

Paper Structure

This paper contains 21 sections, 6 equations, 7 figures, 2 tables.

Table of Contents

  1. Introduction
  2. Related Works
  3. Preliminaries
  4. Graph Neural Networks
  5. Reinforcement Learning
  6. Methodology
  7. Reinforcement Learning Formulation
  8. Preliminary Structure Recognition (SR) and Functional Block Configuration
  9. R-GCN Circuit Representation Learning
  10. R-GCN and RL-based Floorplanning
  11. Designing Action Space and Masking
  12. State Design
  13. Policy Design
  14. Reward Shaping
  15. RL Training Schedule
  16. ...and 6 more sections

Figures (7)

  • Figure 1: Overview of the automatic layout pipeline.
  • Figure 2: 8-structure OTA circuit schematic with its graph representation. Violet edges are for vertical alignment and black for connectivity. Nodes are colored according to the functional block type.
  • Figure 3: R-GCN architecture for circuit reward prediction.
  • Figure 4: Overview of the RL model, enriched with CNN based feature extractor and policy network.
  • Figure 5: Dead space (left) and wire (right) masks. Darker areas highlight higher rewards regions in the case a block is placed there.
  • ...and 2 more figures