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RISecure-PUF: Multipurpose PUF-Driven Security Extensions with Lookaside Buffer in RISC-V

Chenghao Chen, Xiaolin Zhang, Kailun Qin, Tengfei Wang, Yipeng Shi, Tianyi Huang, Chi Zhang, Dawu Gu

Abstract

RISC-V's limited security features hinder its use in confidential computing and heterogeneous platforms. This paper introduces RISecure-PUF, a security extension utilizing existing Physical Unclonable Functions for key generation and secure protocol purposes. A one-way hash function is integrated to ensure provable security against modeling attacks, while a lookaside buffer accelerates batch sampling and minimizes reliance on error correction codes. Implemented on the Genesys 2 FPGA, RISecure-PUF improves at least $2.72\times$ in batch scenarios with negligible hardware overhead and a maximum performance reduction of $10.7\%$, enabled by reusing the hash function module in integrated environments such as cryptographic engines.

RISecure-PUF: Multipurpose PUF-Driven Security Extensions with Lookaside Buffer in RISC-V

Abstract

RISC-V's limited security features hinder its use in confidential computing and heterogeneous platforms. This paper introduces RISecure-PUF, a security extension utilizing existing Physical Unclonable Functions for key generation and secure protocol purposes. A one-way hash function is integrated to ensure provable security against modeling attacks, while a lookaside buffer accelerates batch sampling and minimizes reliance on error correction codes. Implemented on the Genesys 2 FPGA, RISecure-PUF improves at least in batch scenarios with negligible hardware overhead and a maximum performance reduction of , enabled by reusing the hash function module in integrated environments such as cryptographic engines.

Paper Structure

This paper contains 20 sections, 5 figures, 8 tables.

Table of Contents

  1. Introduction
  2. Background and Related Work
  3. RISC-V Architecture
  4. Physical Unclonable Function
  5. Fuzzy Extractor
  6. Controlled PUF
  7. Modeling Attacks
  8. RISecure-PUF
  9. Design Overview
  10. Lookaside Buffer
  11. PUF Instruction Design
  12. Security Analysis
  13. Attack Vector
  14. Cryptographically Provable Security
  15. Security towards Side Channel Attacks
  16. ...and 5 more sections

Figures (5)

  • Figure 1: Arbiter PUF
  • Figure 2: SRAM PUF
  • Figure 4: RISecure-PUF architecture overview
  • Figure 5: Lookaside buffer for batch sampling
  • Figure 6: Performance evaluation of extra lookaside buffer