GraCo -- A Graph Composer for Integrated Circuits

TL;DR

GraCo addresses the complexity of integrated circuit design by introducing a graph-based reinforcement learning framework that autoregressively builds circuits as graphs, which are converted to netlists and verified with SPICE. The method integrates design expert knowledge via consistency checks and explicit wiring rules, and explores two RL strategies (RLOO and Evolution Strategies) to guide topology and sizing. Empirical results on inverter and NAND2 tasks show substantial efficiency gains over random sampling, with ES achieving roughly 5× fewer sampling steps for the inverter and a 2.5× speed-up for NAND2, while consistency checks improve sampling efficiency and solution quality. The work’s impact lies in enabling flexible, knowledge-informed AI-assisted circuit synthesis that can generalize to larger designs and more complex manufacturing constraints.

Abstract

Designing integrated circuits involves substantial complexity, posing challenges in revealing its potential applications - from custom digital cells to analog circuits. Despite extensive research over the past decades in building versatile and automated frameworks, there remains open room to explore more computationally efficient AI-based solutions. This paper introduces the graph composer GraCo, a novel method for synthesizing integrated circuits using reinforcement learning (RL). GraCo learns to construct a graph step-by-step, which is then converted into a netlist and simulated with SPICE. We demonstrate that GraCo is highly configurable, enabling the incorporation of prior design knowledge into the framework. We formalize how this prior knowledge can be utilized and, in particular, show that applying consistency checks enhances the efficiency of the sampling process. To evaluate its performance, we compare GraCo to a random baseline, which is known to perform well for smaller design space problems. We demonstrate that GraCo can discover circuits for tasks such as generating standard cells, including the inverter and the two-input NAND (NAND2) gate. Compared to a random baseline, GraCo requires 5x fewer sampling steps to design an inverter and successfully synthesizes a NAND2 gate that is 2.5x faster.

Figures (6)

• Figure 1: Auto-regressive graph generation in GraCo. At each step, it decides whether to add an internal net, insert a component, or stop the generation process. As an example, we illustrate the design of an inverter consisting of an NMOS and a PMOS transistor.
• Figure 2: Overall framework of GraCo. As an example, we show the design of an inverter with a NMOS and PMOS transistor.
• Figure 3: Bounds on NAND2 topology design space size (solid: upper bound, dashed: lower bound). Orange curves show the original design space, while blue curves reflect the effect of explicit wiring rules.
• Figure 4: Two examples of consistency checks. These checks are used to ensure that the sampled graphs represent valid circuits.
• Figure 5: Distribution of sampling steps and wall clock time to find the standard inverter cell (reward = $1$). Each method was run $30$ times. Red circles mark failures by the random baseline or RLOO. Orange and green lines show median values for successful runs and all runs (including failures which iterated until the limit of $1024$ steps).