MORE-Stress: Model Order Reduction based Efficient Numerical Algorithm for Thermal Stress Simulation of TSV Arrays in 2.5D/3D IC

TL;DR

More-Stress is proposed, a novel strict numerical algorithm for efficient thermal stress simulation of TSV arrays based on model order reduction that can realize a 153–504 x reduction in computational time and a 39-115x reduction in memory usage compared with the commercial software ANSYS.

Abstract

Thermomechanical stress induced by through-silicon vias (TSVs) plays an important role in the performance and reliability analysis of 2.5D/3D ICs. While the finite element method (FEM) adopted by commercial software can provide accurate simulation results, it is very time- and memory-consuming for large-scale analysis. Over the past decade, the linear superposition method has been utilized to perform fast thermal stress estimations of TSV arrays, but it suffers from a lack of accuracy. In this paper, we propose MORE-Stress, a novel strict numerical algorithm for efficient thermal stress simulation of TSV arrays based on model order reduction. Extensive experimental results demonstrate that our algorithm can realize a 153-504 times reduction in computational time and a 39-115 times reduction in memory usage compared with the commercial software ANSYS, with negligible errors less than 1%. Our algorithm is as efficient as the linear superposition method, with an order of magnitude smaller errors and fast convergence.

Figures (6)

• Figure 1: Schematic of a typical 2.5D/3D IC with multi-scale character. Numerous local fine structures are embedded in the system, such as TSVs, micro bumps, die-to-die interconnects, etc. These fine structures render full-system thermal stress simulation by conventional FEM extremely expensive.
• Figure 2: Sectional view and top view of the TSV structure adopted in this paper li2013accurate. It consists of a copper TSV body in the silicon substrate and a dielectric liner. $d$ denotes the diameter of the TSV, $h$ denotes the height, $t$ denotes the thickness of the liner, and $p$ denotes the pitch of adjacent TSVs.
• Figure 3: Illustration of the one-shot local stage, which will be performed only once for a certain set of material and geometry parameters. (a)(b) The material and geometry parameters of the TSV structures to be studied in a certain 2.5D/3D IC are extracted and the unit TSV block is set up. (c) Lagrange interpolation points are added to the surface of the unit block for reduced order modeling, and a fine mesh is developed for the unit block to assemble the local problem. (d) Reduced order model of the unit TSV block is obtained and ready to be applied to the global stage.
• Figure 4: Illustration of the global stage, which will performed every time given a new problem. Once the one-shot local stage is performed, thermal stress of TSV arrays with arbitrary array sizes, under arbitrary thermal loads, and at arbitrary locations in a package system can be efficiently calculated in the global stage. (a) The corresponding pre-calculated reduced order model is loaded. (b)--(d) A standard assembly procedure is applied to assemble the global problem.
• Figure 5: (a) The first scenario. TSV arrays with array sizes ranging from $10\times10$ to $50\times50$ are studied. Except for efficiency and accuracy, this scenario is designed to test the scalability and convergence of our algorithm. (b) The second scenario is a $15\times15$ TSV array embedded at five different locations in a chiplet. This scenario is designed to test the combination of our algorithm with the sub-modeling technique.