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Distributed quantum logic algorithm

Boris Arseniev

TL;DR

A method for reducing circuit depth by introducing auxiliary qubits to enable parallel gate execution is examined, potentially enhancing the performance of quantum simulations on near-term quantum devices and offering advantages for distributed quantum computing.

Abstract

Parallel computation enables multiple processors to execute different parts of a task simultaneously, improving processing speed and efficiency. In quantum computing, parallel gate implementation involves executing gates independently in different registers, directly impacting the circuit depth, the number of sequential quantum gate operations, and thus the algorithm execution time. This work examines a method for reducing circuit depth by introducing auxiliary qubits to enable parallel gate execution, potentially enhancing the performance of quantum simulations on near-term quantum devices. We show that any circuit on $n$ qubits with depth $O\left(M n^2\right)$, where $M = M(n)$ is some function of $n$, can be transformed into a circuit with depth $O\left(\log_2(M) n^2\right)$ operating on $O\left(M n\right)$ qubits. This technique may be particularly useful in noisy environments, where recent findings indicate that only the final $O\left(\log n\right)$ layers influence the expectation value of observables. It may also optimize Trotterization by exponentially reducing the number of Trotter steps. Additionally, the method may offer advantages for distributed quantum computing, and the intuition of treating quantum states as gates and operators as vectors used in this work may have broader applications in quantum computation.

Distributed quantum logic algorithm

TL;DR

A method for reducing circuit depth by introducing auxiliary qubits to enable parallel gate execution is examined, potentially enhancing the performance of quantum simulations on near-term quantum devices and offering advantages for distributed quantum computing.

Abstract

Parallel computation enables multiple processors to execute different parts of a task simultaneously, improving processing speed and efficiency. In quantum computing, parallel gate implementation involves executing gates independently in different registers, directly impacting the circuit depth, the number of sequential quantum gate operations, and thus the algorithm execution time. This work examines a method for reducing circuit depth by introducing auxiliary qubits to enable parallel gate execution, potentially enhancing the performance of quantum simulations on near-term quantum devices. We show that any circuit on qubits with depth , where is some function of , can be transformed into a circuit with depth operating on qubits. This technique may be particularly useful in noisy environments, where recent findings indicate that only the final layers influence the expectation value of observables. It may also optimize Trotterization by exponentially reducing the number of Trotter steps. Additionally, the method may offer advantages for distributed quantum computing, and the intuition of treating quantum states as gates and operators as vectors used in this work may have broader applications in quantum computation.

Paper Structure

This paper contains 13 sections, 4 theorems, 36 equations, 3 figures.

Table of Contents

  1. Introduction
  2. Building blocks of the algorithm
  3. Vectorization
  4. Gathering
  5. Multiplication
  6. Circuit for the algorithm
  7. Distributed quantum logic algorithm
  8. Vectorization stage
  9. Gathering stage
  10. Multiplication stage
  11. Implementation of $G_u$ and $V_u$
  12. Probability of getting the state
  13. Conclusion

Key Result

Proposition 1

Consider a quantum circuit with two gates, $U_1$ and $U_2$, each of size $N \times N$, acting on an initial state $\ket{\Vec{v}}$. The circuit for parallel implementation can be expressed as: where $V = I_{N} \otimes V_u$, and $V_u$ is a unitary matrix whose first row is given by $\ket{\Vec{v}}^T$. The terms $\ket{\vec{r}_{k}}$ represent residual vectors, and $\ket{ {\operatorname{vec}\left(I_N\r

Figures (3)

  • Figure 1: Figure (a) is circuit of 2 gates implemented sequentially, while (b) is the same circuit but implemented in parallel.
  • Figure 2: Circuit for parallel computation of $M = 14$ gates. The vectorization stage is highlighted by the green rectangle, while the gathering stage is represented by three red rectangles: $G_8$, $G_4$, and $G_c$. Here, $G_8$ and $G_4$ are gathering circuits for 8 and 4 gates, respectively, and $G_c$ is the gathering circuit that combines the remainders. The multiplication stage is indicated by the blue rectangle. The desired quantum state is illustrated on the right.
  • Figure 3: Circuit for implementation $\frac{1}{N} G_u = \frac{1}{2} \left(I -e^{i \frac{\pi}{N} G_u}\right)$, where $G_u$ is of size $N^2 \times N^2$, with $N=2^n$ and $n=3$. Here $C^2Z$ implemented as $(I \otimes I \otimes H) C^2X (I \otimes I \otimes H)$.

Theorems & Definitions (4)

  • Proposition 1: 2 parallel gates
  • Proposition 2: Distributed Qubit Logic (DQL)
  • Proposition 3: Implementation of $G_u$ and $V_u$
  • Corollary 1: Efficient parallelization