An Efficient Multicast Addressing Encoding Scheme for Multi-Core Neuromorphic Processors

TL;DR

This work proposes a hierarchical bit string encoding scheme that largely expands the addressing capability of state-of-the-art symbol-based schemes for the same number of routing bits, and achieves a reduction in area cost and energy consumption.

Abstract

Multi-core neuromorphic processors are becoming increasingly significant due to their energy-efficient local computing and scalable modular architecture, particularly for event-based processing applications. However, minimizing the cost of inter-core communication, which accounts for the majority of energy usage, remains a challenging issue. Beyond optimizing circuit design at lower abstraction levels, an efficient multicast addressing scheme is crucial. We propose a hierarchical bit string encoding scheme that largely expands the addressing capability of state-of-the-art symbol-based schemes for the same number of routing bits. When put at work with a real neuromorphic task, this hierarchical bit string encoding achieves a reduction in area cost by approximately 29% and decreases energy consumption by about 50%.

Figures (5)

• Figure 1: Top: A diagram depicting multicast routing in multi-core neuromorphic processors. The green neural core serves as the source, containing one or more source neurons, while the blue neural cores represent the target cores, each holding one or more target neurons. Each "[ ]" represents an entry in the LUT for each source neuron, storing the address of the target core. Middle: Illustrates exact routing, which eliminates the need for filtering illegal data packets but requires a larger packet header (shown as wider arrows). Bottom: Shows region-based routing, where illegal data packets in non-target cores (shown as red cores) must be filtered out.
• Figure 2: Determining the number of nodes at each hierarchical level.
• Figure 3: A comparison of the scalability of various multicast addressing encoding schemes.
• Figure 4: HBS mapping in a NoC with a hierarchical tree topology. Top: The illustration shows an example without illegal multicast. The green core indicates the source core, while the blue cores represent the target cores. The routing logic remains consistent across all R1 data switches, as depicted in the top right corner. $Up$ signifies selecting the $Up$ output port for the upward path, and $D$ indicates choosing the corresponding $Down$ output port for the downward path. Bottom: This example demonstrates a scenario with illegal multicast. The red cores highlight those responsible for filtering out illegal spike data packets.
• Figure 5: The NoC area cost and energy consumption in the real SNN task across various encoding schemes.