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Timing-driven Approximate Logic Synthesis Based on Double-chase Grey Wolf Optimizer

Xiangfei Hu, Yuyang Ye, Tinghuan Chen, Hao Yan, Bei Yu

TL;DR

This paper proposes an effective timing-driven ALS framework, where it employs a double-chase grey wolf optimizer to explore and apply LACs, simultaneously bringing excellent critical path shortening and area reduction under error constraints.

Abstract

With the shrinking technology nodes, timing optimization becomes increasingly challenging. Approximate logic synthesis (ALS) can perform local approximate changes (LACs) on circuits to optimize timing with the cost of slight inaccuracy. However, existing ALS methods that focus solely on critical path depth reduction (depth-driven methods) or area minimization (area-driven methods) are inefficient in achieving optimal timing improvement. %based on double-chase grey wolf optimizer (DCGWO). where we employ a double-chase grey wolf optimizer to explore and apply LACs, simultaneously bringing excellent critical path shortening and area reduction under error constraints. According to experiments on open-source circuits with TSMC 28nm technology, compared to the SOTA method, our framework can generate approximate circuits with greater critical path delay reduction under different error and area constraints.

Timing-driven Approximate Logic Synthesis Based on Double-chase Grey Wolf Optimizer

TL;DR

This paper proposes an effective timing-driven ALS framework, where it employs a double-chase grey wolf optimizer to explore and apply LACs, simultaneously bringing excellent critical path shortening and area reduction under error constraints.

Abstract

With the shrinking technology nodes, timing optimization becomes increasingly challenging. Approximate logic synthesis (ALS) can perform local approximate changes (LACs) on circuits to optimize timing with the cost of slight inaccuracy. However, existing ALS methods that focus solely on critical path depth reduction (depth-driven methods) or area minimization (area-driven methods) are inefficient in achieving optimal timing improvement. %based on double-chase grey wolf optimizer (DCGWO). where we employ a double-chase grey wolf optimizer to explore and apply LACs, simultaneously bringing excellent critical path shortening and area reduction under error constraints. According to experiments on open-source circuits with TSMC 28nm technology, compared to the SOTA method, our framework can generate approximate circuits with greater critical path delay reduction under different error and area constraints.

Paper Structure

This paper contains 12 sections, 9 equations, 8 figures, 3 tables.

Figures (8)

  • Figure 1: Optimizing circuit by wire-by-wire (substitute a wire with another wire in circuits) and wire-by-constant (substitute a wire with constant logic value '0'$/$'1') LACs. Area reductions are converted into drive strength enhancement of gates.
  • Figure 2: The overall flow of our timing-driven approximate logic synthesis framework based on double-chase grey wolf optimizer.
  • Figure 3: Circuit representation based on gate fan-in adjacency.
  • Figure 4: Population division. Population is divided into leader $c_l$, elite circuits $\mathcal{G}_{e}$, and $\omega$ circuits group $\mathcal{G}_\omega$ based on fitness, with each hierarchy engaging in distinct chase operations.
  • Figure 5: Illustrations of the circuit searching, circuit reproduction, and optimization gradients guided by them in double-chase.
  • ...and 3 more figures