How to Build a Quantum Supercomputer: Scaling from Hundreds to Millions of Qubits

TL;DR

The paper argues that reaching utility-scale quantum computing requires a full-stack, HPC-integrated approach that couples fault-tolerant quantum processors with classical control, data management, and software ecosystems. It outlines a concrete architecture across fabrication, wafer-scale integration, real-time control, FTQC tooling, and hybrid quantum–classical workflows, and provides detailed resource-estimation results for chemistry applications to illustrate practical implications. Key findings show that gate fidelities, error distributions, and fast, low-latency decoding are critical bottlenecks, while distributed FTQC and circuit-knitting-based workload distribution offer viable pathways to scale before full fault-tolerance is achieved. The work further explores near-term distributed quantum simulations, quantum-inspired probabilistic computing, and cost-reduction strategies via existing semiconductor supply chains, presenting a holistic, systemic vision for realizing quantum utility at scale.

Abstract

In the span of four decades, quantum computation has evolved from an intellectual curiosity to a potentially realizable technology. Today, small-scale demonstrations have become possible for quantum algorithmic primitives on hundreds of physical qubits and proof-of-principle error-correction on a single logical qubit. Nevertheless, despite significant progress and excitement, the path toward a full-stack scalable technology is largely unknown. There are significant outstanding quantum hardware, fabrication, software architecture, and algorithmic challenges that are either unresolved or overlooked. These issues could seriously undermine the arrival of utility-scale quantum computers for the foreseeable future. Here, we provide a comprehensive review of these scaling challenges. We show how the road to scaling could be paved by adopting existing semiconductor technology to build much higher-quality qubits, employing system engineering approaches, and performing distributed quantum computation within heterogeneous high-performance computing infrastructures. These opportunities for research and development could unlock certain promising applications, in particular, efficient quantum simulation/learning of quantum data generated by natural or engineered quantum systems. To estimate the true cost of such promises, we provide a detailed resource and sensitivity analysis for classically hard quantum chemistry calculations on surface-code error-corrected quantum computers given current, target, and desired hardware specifications based on superconducting qubits, accounting for a realistic distribution of errors. Furthermore, we argue that, to tackle industry-scale classical optimization and machine learning problems in a cost-effective manner, heterogeneous quantum-probabilistic computing with custom-designed accelerators should be considered as a complementary path toward scalability.

Figures (46)

• Figure 1: Schematic plot of the number of qubits from three experiments at UCSB and Google over time, which describes a Moore's law growth in the number of qubits. After the quantum supremacy experiment in 2019 arute2019quantum, a target of one million qubits at the end of the decade was projected by industry leaders. However, the current pace of hardware progress Acharya2024 suggests that goal might be postponed by several decades, assuming an optimistic scenario that none of the scaling challenges mentioned here slows or halts the progress. To arrive at utility-scale quantum computers in the 2030--2035 time frame, a major increase in the rate of progress over the next five years is needed. Our thesis is that new fabrication and systems design as well as full-stack HPC integration are required to tackle this challenge. For estimates of future scaling, we suggest using the number of qubits that can be entangled in practice (which assumes sufficient qubit connectivity with multi-qubit gates that are fast and accurate enough) cao2023entanglement.
• Figure 2: Architecture diagram of a quantum--classical full-stack solution. Extensions within the HPC programming environment include a quantum interface library for seamless invocation of quantum kernels, an adaptive circuit knitting hypervisor for efficient quantum workload partitioning and distribution, and quantum compiler and runtime extension for performant quantum circuit compilation. A customized hybrid workload manager ensures maximal quantum resource utilization in a multi-user environment. For fault-tolerant quantum computation, a compiler, emulator, assembler, and real-time decoder work together to use hardware noise profiles to synthesize optimized fault-tolerant circuits. Calibration and control of quantum resources use specialized hardware and are integrated with HPC. At the hardware layer, heterogeneous coprocessors include CPUs/GPUs, quantum processing units (QPU), probabilistic processing units (PPU), FPGA and custom-design ASICs with high-speed low-latency scale-up interconnect.
• Figure 3: Architecture of two nodes in an accelerated quantum supercomputer. AI superchips are coupled to QPUs via low-latency quantum--classical interconnects and quantum control hardware. AI superchips communicate via classical HPC interconnects, while QPUs are connected by quantum interconnects.
• Figure 4: IBM Heron (Fez) device performance taken on 08/06/2024 from calibration data accessible via IBM's quantum cloud. (a) Distribution of $T_1$ across 155 qubits. (b) Distribution of two-qubit (2q) error rates across 351 qubit pairs.
• Figure 5: Illustration with simulated data on how the effect of fabrication uniformity and qubit size on median qubit error. (a) When selecting from a small number of qubits, it is possible to cherry pick the best qubits on the wafer and avoid outliers. (b) When selecting from 300+ qubits, it is impossible to avoid fabrication outliers.