AMARETTO: Enabling Efficient Quantum Algorithm Emulation on Low-Tier FPGAs

TL;DR

Validating quantum algorithms is hindered by noise on real devices and the computational burden of software simulators. This work presents AMARETTO, a RISC-like FPGA quantum emulator that exploits a butterfly-based amplitude selection and a $20$-bit fixed-point representation to emulate Clifford+T and rotational gates, compiling OpenQASM 2.0 into a compact 32-bit instruction stream. The architecture supports a universal gate set on low-tier FPGAs and demonstrates up to $16$ qubits on an AMD Kria KV260, achieving substantial speedups over software and avoiding re-synthesis for new circuits. Functional validation against Qiskit shows close agreement (GCD $<0.05$) and hardware-based emulation runs orders of magnitude faster, enabling practical quantum algorithm verification on affordable hardware and accelerating quantum software development.

Abstract

Researchers and industries are increasingly drawn to quantum computing for its computational potential. However, validating new quantum algorithms is challenging due to the limitations of current quantum devices. Software simulators are time and memory-consuming, making hardware emulators an attractive alternative. This article introduces AMARETTO (quAntuM ARchitecture EmulaTion TechnOlogy), designed for quantum computing emulation on low-tier Field-Programmable gate arrays (FPGAs), supporting Clifford+T and rotational gate sets. It simplifies and accelerates the verification of quantum algorithms using a Reduced-Instruction-Set-Computer (RISC)-like structure and efficient handling of sparse quantum gates. A dedicated compiler translates OpenQASM 2.0 into RISC-like instructions. AMARETTO is validated against the Qiskit simulators. Our results show successful emulation of sixteen qubits on a AMD Kria KV260 SoM. This approach rivals other works in emulated qubit capacity on a smaller, more affordable FPGA

Figures (5)

• Figure 1: Example of a two-qubit quantum circuit, highlighting with dotted vertical lines the different layers and showing on the top the state vector evolution layer by layer.
• Figure 2: The butterfly-like mechanism for selecting interacting couples of probability amplitudes in a two-qubit system.
• Figure 3: AMARETTO g-type instruction, separating the fields.
• Figure 4: AMARETTO architecture and high-level scheme of its emulation environment.
• Figure 5: Comparison of execution time between Qiskit simulators and AMARETTO, showing hardware emulation's significant advantage over software.