Reducing ADC Front-end Costs During Training of On-sensor Printed Multilayer Perceptrons
Florentia Afentaki, Paula Carolina Lozano Duarte, Georgios Zervakis, Mehdi B. Tahoori
TL;DR
This work targets the high area and power burden of ADCs in on-sensor printed MLP classifiers by introducing bespoke pruned flash ADCs per sensor input. It combines a Python-based partial-ADC area proxy with NSGA-II optimization and quantization-aware training to prune unnecessary representation levels while maintaining accuracy, formalized through per-input level masks and $2^N$ level budgets. The approach achieves substantial hardware reductions, reporting an average $11.2\times$ ADC area reduction and $13.2\times$ power reduction with under $5\%$ accuracy loss, outperforming state-of-the-art area-efficient designs when ADC costs are included. This ADC-aware training framework enhances practical viability of ultra-low-cost, on-sensor printed ML systems and can be applied on top of other MLP approximation strategies.
Abstract
Printed electronics technology offers a cost-effectiveand fully-customizable solution to computational needs beyondthe capabilities of traditional silicon technologies, offering ad-vantages such as on-demand manufacturing and conformal, low-cost hardware. However, the low-resolution fabrication of printedelectronics, which results in large feature sizes, poses a challengefor integrating complex designs like those of machine learn-ing (ML) classification systems. Current literature optimizes onlythe Multilayer Perceptron (MLP) circuit within the classificationsystem, while the cost of analog-to-digital converters (ADCs)is overlooked. Printed applications frequently require on-sensorprocessing, yet while the digital classifier has been extensivelyoptimized, the analog-to-digital interfacing, specifically the ADCs,dominates the total area and energy consumption. In this work,we target digital printed MLP classifiers and we propose thedesign of customized ADCs per MLP's input which involvesminimizing the distinct represented numbers for each input,simplifying thus the ADC's circuitry. Incorporating this ADCoptimization in the MLP training, enables eliminating ADC levelsand the respective comparators, while still maintaining highclassification accuracy. Our approach achieves 11.2x lower ADCarea for less than 5% accuracy drop across varying MLPs.