Table of Contents
Fetching ...

System-Level Analysis for mm-Wave Full-Duplex Transceivers

Mohamad Mahdi Rajaei Rizi, Jeyanandh Paramesh, Kamran Entesari

Abstract

This paper conducts a comprehensive system-level analysis of mm-Wave full-duplex transceivers, focusing on a receiver employing a four-stage self-interference cancellation (SIC) process. The analysis aims to optimize the noise and linearity performance requirements of each transceiver block, ensuring that the self-interference (SI) signal does not compromise the receiver's error vector magnitude (EVM) for an OFDM 64-QAM signal. Additionally, the necessary SIC for each stage is calculated to establish feasible noise and linearity specifications for a CMOS-based implementation. The resulting specifications are subsequently validated within a MATLAB Simulink environment, confirming the accuracy of the computed requirements for each block.

System-Level Analysis for mm-Wave Full-Duplex Transceivers

Abstract

This paper conducts a comprehensive system-level analysis of mm-Wave full-duplex transceivers, focusing on a receiver employing a four-stage self-interference cancellation (SIC) process. The analysis aims to optimize the noise and linearity performance requirements of each transceiver block, ensuring that the self-interference (SI) signal does not compromise the receiver's error vector magnitude (EVM) for an OFDM 64-QAM signal. Additionally, the necessary SIC for each stage is calculated to establish feasible noise and linearity specifications for a CMOS-based implementation. The resulting specifications are subsequently validated within a MATLAB Simulink environment, confirming the accuracy of the computed requirements for each block.

Paper Structure

This paper contains 10 sections, 29 equations, 4 figures, 1 table.

Figures (4)

  • Figure 1: A full-duplex communication link.
  • Figure 2: Full-duplex transceiver block-diagram at UE end.
  • Figure 3: (a) Simulation setup implemented in Simulink to extract the correction factor (b) Input spectrum with 400 MHz and -47.4 dBm occupied bandwidth and average channel power, respectively. (c) Output spectrum of the setup signifying a channel power level of -114.7 dBm for the IM3 products. (d) Input-referred power level of IM3 products versus input power, the blue curve represents the simulation results and red curve is the predicted value by (\ref{['iip3_eq']}).
  • Figure 4: (a) The track of simulated power levels for desired signal, SI, IM3 product generated by RX, IM3 product generated by UE's PA, and noise through the link chain ($\text{SIC}_{\text{1}}=\text{40\,dB}$, $\text{SIC}_{\text{2}}=\text{28\,dB}$, $\text{SIC}_{\text{3}}=\text{16\,dB}$, $\text{SIC}_{\text{4}}=\text{10\,dB}$, $\text{NF}_{\text{RX}}=\text{8\,dB}$, $\text{IIP}_{\text{3-LNA}}=\text{-7\,dBm}$, $\text{IIP}_{\text{3-Mixer}}=\text{0\,dBm}$, $\text{IIP}_{\text{3-BBAmp}}=\text{+5\,dBm}$, and $\text{OP}_{\text{1dB-PA(UE)}}=\text{+15\,dBm}$). (b) Simulated constellation of the signal from the BS end; the resulted $\%\text{EVM}_{\text{rms}}$ is $\%$3. (c) Simulated constellation of the entire link; the resulted $\%\text{EVM}_{\text{rms}}$ is $\%$9.