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Web-Based Simulator of Superscalar RISC-V Processors

Jiri Jaros, Michal Majer, Jakub Horky, Jan Vavra

TL;DR

This advanced simulator empowers both IT students and professionals to grasp the fundamentals of superscalar RISC-V processors, HW/SW co-design and HPC optimization techniques.

Abstract

Mastering computational architectures is essential for developing fast and power-efficient programs. Our advanced simulator empowers both IT students and professionals to grasp the fundamentals of superscalar RISC-V processors, HW/SW co-design and HPC optimization techniques. With customizable processor and memory architecture, full C compiler support, and detailed runtime statistics, this tool offers a comprehensive learning experience. Enjoy the convenience of a modern, web-based GUI to enhance your understanding and skills.

Web-Based Simulator of Superscalar RISC-V Processors

TL;DR

This advanced simulator empowers both IT students and professionals to grasp the fundamentals of superscalar RISC-V processors, HW/SW co-design and HPC optimization techniques.

Abstract

Mastering computational architectures is essential for developing fast and power-efficient programs. Our advanced simulator empowers both IT students and professionals to grasp the fundamentals of superscalar RISC-V processors, HW/SW co-design and HPC optimization techniques. With customizable processor and memory architecture, full C compiler support, and detailed runtime statistics, this tool offers a comprehensive learning experience. Enjoy the convenience of a modern, web-based GUI to enhance your understanding and skills.

Paper Structure

This paper contains 17 sections, 12 figures, 1 table.

Table of Contents

  1. Introduction
  2. State of the Art
  3. Objectives
  4. Key Features of the Simulator
  5. Main Window with the Processor View
  6. Code Editor
  7. Memory and Processor Architecture Settings
  8. Runtime Statistics
  9. Command-Line Interface
  10. Implementation and Deployment
  11. Simulator Architecture and Simulation Step Manager
  12. Register Representation and Instruction Interpretation
  13. Compiler Integration
  14. Deployment
  15. Testing and Evaluation
  16. ...and 2 more sections

Figures (12)

  • Figure 1: Graphical representation of the fetch block with (1) block name, (2) simulation information, (3) active instructions, (4) pop-up details, and (5) resize bar."
  • Figure 2: A pop-up window displaying the current state of the memory, including allocated arrays, their starting addresses, and a memory dump."
  • Figure 3: A pop-up window that displays instruction current state, parameters, renaming details, values and validity, along with instruction flags and the timestamps of phase completions.
  • Figure 4: Code editor displaying C and Assembly codes, with compiler parameters and control buttons.
  • Figure 5: Code editor showing the link between C and Assembly codes, with instruction details displayed in a bubble window.
  • ...and 7 more figures