Skipped Adjacency Pulse Width Modulation: Zero Voltage Switching over Full Duty Cycle Range for Hybrid Flying Capacitor Multi-Level Converters without Dynamic Level Changing

Abstract

This paper proposes a method to achieve zero voltage switching (ZVS) across the full duty cycle range in hybrid flying capacitor multilevel (FCML) converters, eliminating the need for dynamic level changing and active re-balancing. Utilizing skipped adjacency pulse width modulation (SAPWM), this approach avoids the nearest pole voltage level, thereby increasing volt-seconds within specific duty cycle range. The method uses a modified PWM scheme, which preserves effective pole voltage by changing duty reference and employing digital logic processing. Simulation results verify the proposed method achieving full-range ZVS. This SAPWM technique is compatible with hybrid FCML converters with various levels, offering enhanced efficiency and reduced switching losses.

Figures (13)

• Figure 1: Circuit diagram of hybrid FCML topology.
• Figure 2: Inductor current waveform indicating ZVS and hard switching under two different switching frequencies.
• Figure 3: Equivalent LC resonant circuit between the switch output capacitors and inductor under PSPWM during dead-time.
• Figure 4: Variable frequency profile for ZVS under PSPWM and SAPWM, given parameters: $I_{ZVS} = 1$ A, $|i_L| = 3$ A, $L = 4.4$$\mu$H, $V_{in} = 400$ V, and $N = 6$. The lower bound of switching frequency is 70 kHz.
• Figure 5: Current control result with PSPWM and variable switching frequency, including a lower bound of 70 kHz for switching frequency.