Project Tracyn: Generative Artificial Intelligence based Peripherals Trace Synthesizer

TL;DR

Tracyn addresses the need for realistic, constraint-consistent PCIe TLP traces by reframing trace synthesis as image generation. It couples a backbone generative AI with a dispersion-based, image-informed calibration pipeline (normalization, calibration, decoding) to enforce PCIe-specific ordering and causality. Empirical results show up to $1000\times$ improvement on task-specific metrics and up to $2.19\times$ improvement in $FID$ over backbone-only methods, with robust convergence when using strong backbones and embedding-based calibration. The approach enables scalable, controllable trace generation for device prototyping and hardware-software co-design, and the work is released open-source for public use.

Abstract

Peripheral Component Interconnect Express (PCIe) is the de facto interconnect standard for high-speed peripherals and CPUs. Prototyping and optimizing PCIe devices for emerging scenarios is an ongoing challenge. Since Transaction Layer Packets (TLPs) capture device-CPU interactions, it is crucial to analyze and generate realistic TLP traces for effective device design and optimization. Generative AI offers a promising approach for creating intricate, custom TLP traces necessary for PCIe hardware and software development. However, existing models often generate impractical traces due to the absence of PCIe-specific constraints, such as TLP ordering and causality. This paper presents Phantom, the first framework that treats TLP trace generation as a generative AI problem while incorporating PCIe-specific constraints. We validate Phantom's effectiveness by generating TLP traces for an actual PCIe network interface card. Experimental results show that Phantom produces practical, large-scale TLP traces, significantly outperforming existing models, with improvements of up to 1000$\times$ in task-specific metrics and up to 2.19$\times$ in Frechet Inception Distance (FID) compared to backbone-only methods.

Figures (6)

• Figure 1: Topology of PCIe Devices in Modern Computing Systems. This diagram models a PCIe network interface card, highlighting key concepts like Transaction Layer Packet (TLP), Memory-Mapped Input/Output (MMIO), Direct Memory Access (DMA), Message Signaled Interrupt (MSI), and the transmit (TX) and receive (RX) pathways. It also includes examples of text-based traces, detailing the patterns and constraints. Proper synthesis of TLP traces requires addressing PCIe TLP constraints, such as ordering and causality, necessitating domain expertise.
• Figure 2: Overview of Tracyn. The architecture of Tracyn follows a 1+3 stage pipeline: generation, normalization, calibration, and decoding. Stage 0. Content Generation: The backbone generative AI model produces the initial content. Stage 1. Content Normalization: The content is normalized and defects are removed using the TLP trace visualization encoding method (See Section \ref{['sec:Visual Encoding and Decoding of TLP Traces']}). Stage 2. Content Calibration: The normalized content is corrected using a dispersion-based calibration method (See Section \ref{['sec:Dispersion-Based Calibration Method']}) to ensure accuracy and consistency. Stage 3. Decoding: The calibrated content is decoded to produce the final output using the same visualization encoding method.
• Figure 3: Comparison of Raw Content, Prior Knowledge, and Tracyn Output. Each unit shows the process applied to different generative AI models. The upper-left quadrant displays the raw content (R), the lower-left shows ground truth (GT), and the right side presents Tracyn's final output (P). Significant differences are marked with red boxes, highlighting how Tracyn selectively integrates patterns from the raw content and prior knowledge.
• Figure 4: Heatmap of Transmission Traffic Errors ($\mathit{TE}$). Each heatmap cell represents the logarithm of the $\mathit{TE}$. Darker colors indicate greater improvement in $\mathit{TE}$ accuracy. If $\mathit{TE}$ is eliminated, it is marked with a '✓'.
• Figure 5: Improvements Attained from Tracyn's Components. When prioritizing transmission traffic error, a fully implemented Tracyn can achieve up to a 98.19% improvement compared to the backbone generator alone.