Optimizing Multi-level Magic State Factories for Fault-Tolerant Quantum Architectures

TL;DR

This work tackles resource estimation for fault-tolerant quantum computing by designing a modular architecture that couples a Core Processor with a multi-level Magic State Factory (MSF). It introduces a bi-objective optimization and a fast heuristic to balance space (physical qubits) and time (runtime) under a global error budget, reducing resource prediction to a small set of parameters $(α,β,μ,Λ,γ)$ and circuit/hardware characteristics. Through numerical studies (e.g., FeMoco-76) the authors illuminate Pareto-front trade-offs, showing how reaction time, memory-suppression, and distillation structure shape qubit counts and runtimes across regimes from time-optimal to space-optimal. The framework provides actionable estimates for utility-scale quantum algorithms, highlighting significant space-time trade-offs and the potential to adapt to various resource-state factories beyond magic states.

Abstract

We propose a novel technique for optimizing a modular fault-tolerant quantum computing architecture, taking into account any desired space-time trade-offs between the number of physical qubits and the fault-tolerant execution time of a quantum algorithm. We consider a concept architecture comprising a dedicated zone as a multi-level magic state factory and a core processor for efficient logical operations, forming a supply chain network for production and consumption of magic states. Using a heuristic algorithm, we solve the multi-objective optimization problem of minimizing space and time subject to a user-defined error budget for the success of the computation, taking the performance of various fault-tolerant protocols into account. As an application, we show that physical quantum resource estimation reduces to a simple model involving a small number of key parameters, namely, the circuit volume, the error prefactors ($μ$) and error suppression rates ($Λ$) of the fault-tolerant protocols, the reaction time ($γ$), and an allowed slowdown factor ($β$).

Figures (9)

• Figure 1: Example layout of the core processor. The memory fabric is composed of $Q = 18$ logical qubits distributed in nine two-tile, two-qubit data patches surrounded by bus patches, while the buffer is composed of patches dedicated to storing magic states produced in the MSF. This storage space is designed to allow post-corrected $\pi/8$ rotations by connecting the magic state growth patches to a correction qubit patch using lattice surgery in parallel to the lattice surgery used to connect the data patches to the magic state consumed in a magic state storage patch. Magic state growth patches also allow magic state expansion if the produced magic states are of a different size than is required. The sides of the buffer are used to store correction qubits. The number of correction storage patches is determined by the time required to perform the classical processing in the post-corrected protocol.
• Figure 2: Architecture of the MSF and its interface with the core processor buffer. Magic states are prepared using dedicated preparation units following a preparation protocol. Once preparation succeeds, magic states wait until a storage patch is available and then are moved to there using patch deformation. When in a storage patch, a similar post-correction protocol as is performed in the buffer follows, where a correction qubit is created, entangled with the magic state, and stored. The magic state is then used for the $\pi/8$ rotations performed between this magic state and data and distilling port qubits within the distillation unit. The higher-fidelity magic states are prepared in the distilling ports of these units. Once ready, they proceed to growth units dedicated to a next-level distillation unit. The process repeats until the highest level sends a magic state to the core processor. In this example, two distillation levels are represented for 15:1 distillation protocols, composed of three and two distillation units each from lowest to highest. While the lower-level unit design allows distillation of higher-fidelity magic states every 13 logical cycles if enough preparation units are available, topological limitations make the higher-level unit distill magic states only every 15 logical cycles instead due to the extra time required to load magic states into the data qubits before a distillation cycle begins.
• Figure 3: Space and time cost estimates for varying magic state factory sizes. Estimates for the FeMoco-76 circuit with $T = 1.4 \times 10^{13}$ and $Q = 1972$m and quantum computers with $\Lambda_{\text{mem}} = 9.3$. The Pareto frontier points are highlighted, indicating the optimal solutions for the assembly problem. The point where $\beta = 1$ represents the serial scheduling case. The points to the left of $\beta = 1$ assume different degrees of circuit parallelization, while those to the right reflect increasing $\beta$ values until all distillation levels have only one unit. The two sharp increases in the physical qubit counts are due to increases in code distances in the core processor needed to meet the error budget at extended idling times.
• Figure 4: (a) Pareto frontier estimates are shown for combinations of $T$-count $T = 10^6$ to $10^{15}$ and logical data qubits $Q = 10^2$ to $10^4$ in a quantum circuit, based on an FTQC model with a quantum memory error prefactor of $\mu_{\text{mem}} = 1.9 \times 10^{-2}$, an error suppression rate of $\Lambda_{\text{mem}} = 9.3$, and a magic state preparation error rate of $e_{\text{prep}} = 4.73 \times 10^{-5}$. While runtime is heavily influenced by the number of non-Clifford gates in the circuit and the MSF size, these estimates demonstrate that quantum computers require between $10^5$ and $10^8$ physical qubits across all scenarios evaluated. (b) Pareto frontier estimates for combinations of $\Lambda_{\text{mem}} = 3$ to $10$ and a magic state preparation error rate of $e_{\text{prep}} = 10^{-2}$ to $10^{-8}$ for the FeMoco-76 circuit with $T = 1.4 \times 10^{13}$ and $Q = 1972$. The estimates show that improving $\Lambda_{\text{mem}}$ among the scenarios tested can reduce the physical qubit count by up to one order of magnitude with a smaller impact on the expected runtime due to the reduced code distances. Meanwhile, improving $e_{\text{prep}}$ has a small effect on reducing physical qubit count because of the relatively large size of the core processor compared to the MSF, and no effect on the expected runtime.
• Figure 5: Space and time cost estimates for varying reaction times. Estimates for the FeMoco-76 circuit with $T = 1.4 \times 10^{13}$ and $Q = 1972$, and a quantum computer with $\Lambda_{\text{mem}} = 9.3$, for $\beta = 1$. Estimates are generated for reaction times $\gamma$ ranging from 100 ns to 1 s. The plots indicate that, for the hardware specification assumed, reaction-time-limited computation provides speedups when $\gamma \lesssim d_{L+1}W$, which, for the scenario tested with $d_{L+1} = 41$ and $W = 350$ ns, results in the threshold at $14.35 \mu$s. Beyond this threshold, runtime decreases linearly with decreasing reaction time at a linearly increasing space cost. For slower reaction times, $T$-count-limited computation is optimal. However, longer reaction times increase space costs due to the larger correction qubit storage requirements in the buffer and MSF.