Reusable Verification Components for High-Energy Physics readout ASICs

TL;DR

This paper tackles the repetitive yet critical problem of verifying front-end readout ASICs in High-Energy Physics by introducing a suite of reusable UVM-based verification components (UVCs) developed under the CHIPS initiative. The components cover common verification tasks, including clock generation, reset handling, configuration, and hit/fault injections, and are organized as modular UVM environments/agents (Pin, Clock, I2C, Wishbone, Hit, SEE) with extendable sequences and RAL integration. The approach accelerates verification by enabling rapid assembly of robust testbenches and by promoting consistency across multiple projects, as evidenced by successful usage across numerous HEP ASICs. The work provides practical integration guidance and demonstrates real-world applicability through a representative DUT example, with broad distribution via CERN asicsupport to foster community reuse and collaboration.

Abstract

Verification is a critical aspect of designing front-end (FE) readout ASICs for High-Energy Physics (HEP) experiments. These ASICs share several similar functional features, resulting in similar verification objectives, which can be addressed using comparable verification strategies. This contribution presents a set of re-usable verification components for addressing common verification tasks, such as clock generation, reset handling, configuration, as well as hit and fault injections. The components were developed as part of the CHIPS initiative and they have been successfully used in the verification of multiple HEP ASICs.

Figures (1)

• Figure 1: Example of DUT (a) and testbench with the UVCs connected to the DUT (b).