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DP-HLS: A High-Level Synthesis Framework for Accelerating Dynamic Programming Algorithms in Bioinformatics

Yingqi Cao, Anshu Gupta, Jason Liang, Yatish Turakhia

TL;DR

DP-HLS is introduced, a novel framework based on High-Level Synthesis (HLS) that simplifies and accelerates the development of a broad set of bioinformatically relevant DP algorithms in hardware and features an easy-to-use template with integrated HLS directives, enabling efficient hardware solutions without requiring hardware design knowledge.

Abstract

Dynamic programming (DP) based algorithms are essential yet compute-intensive parts of numerous bioinformatics pipelines, which typically involve populating a 2-D scoring matrix based on a recursive formula, optionally followed by a traceback step to get the optimal alignment path. DP algorithms are used in a wide spectrum of bioinformatics tasks, including read assembly, homology search, gene annotation, basecalling, and phylogenetic inference. So far, specialized hardware like ASICs and FPGAs have provided massive speedup for these algorithms. However, these solutions usually represent a single design point in the DP algorithmic space and typically require months of manual effort to implement using low-level hardware description languages (HDLs). This paper introduces DP-HLS, a novel framework based on High-Level Synthesis (HLS) that simplifies and accelerates the development of a broad set of bioinformatically relevant DP algorithms in hardware. DP-HLS features an easy-to-use template with integrated HLS directives, enabling efficient hardware solutions without requiring hardware design knowledge. In our experience, DP-HLS significantly reduced the development time of new kernels (months to days) and produced designs with comparable resource utilization to open-source hand-coded HDL-based implementations and performance within 7.7-16.8% margin. DP-HLS is compatible with AWS EC2 F1 FPGA instances. To demonstrate the versatility of the DP-HLS framework, we implemented 15 diverse DP kernels, achieving 1.3-32x improved throughput over state-of-the-art GPU and CPU baselines and providing the first open-source FPGA implementation for several of them. The DP-HLS codebase is available freely under the MIT license and its detailed wiki is available to assist new users.

DP-HLS: A High-Level Synthesis Framework for Accelerating Dynamic Programming Algorithms in Bioinformatics

TL;DR

DP-HLS is introduced, a novel framework based on High-Level Synthesis (HLS) that simplifies and accelerates the development of a broad set of bioinformatically relevant DP algorithms in hardware and features an easy-to-use template with integrated HLS directives, enabling efficient hardware solutions without requiring hardware design knowledge.

Abstract

Dynamic programming (DP) based algorithms are essential yet compute-intensive parts of numerous bioinformatics pipelines, which typically involve populating a 2-D scoring matrix based on a recursive formula, optionally followed by a traceback step to get the optimal alignment path. DP algorithms are used in a wide spectrum of bioinformatics tasks, including read assembly, homology search, gene annotation, basecalling, and phylogenetic inference. So far, specialized hardware like ASICs and FPGAs have provided massive speedup for these algorithms. However, these solutions usually represent a single design point in the DP algorithmic space and typically require months of manual effort to implement using low-level hardware description languages (HDLs). This paper introduces DP-HLS, a novel framework based on High-Level Synthesis (HLS) that simplifies and accelerates the development of a broad set of bioinformatically relevant DP algorithms in hardware. DP-HLS features an easy-to-use template with integrated HLS directives, enabling efficient hardware solutions without requiring hardware design knowledge. In our experience, DP-HLS significantly reduced the development time of new kernels (months to days) and produced designs with comparable resource utilization to open-source hand-coded HDL-based implementations and performance within 7.7-16.8% margin. DP-HLS is compatible with AWS EC2 F1 FPGA instances. To demonstrate the versatility of the DP-HLS framework, we implemented 15 diverse DP kernels, achieving 1.3-32x improved throughput over state-of-the-art GPU and CPU baselines and providing the first open-source FPGA implementation for several of them. The DP-HLS codebase is available freely under the MIT license and its detailed wiki is available to assist new users.

Paper Structure

This paper contains 31 sections, 13 figures, 2 tables.

Table of Contents

  1. Introduction
  2. Background and Motivation
  3. The 2-D Dynamic Programming Paradigm
  4. Variations in the 2-D DP Paradigm
  5. Sequence Alphabet:
  6. Scoring Equations:
  7. Traceback Strategy:
  8. Search-space Pruning Heuristics:
  9. An Overview of the DP-HLS Framework
  10. Front-end Implementation
  11. Back-end Implementation
  12. Scoring Logic Design
  13. Traceback Logic and Memory Design
  14. Parallel Execution of Kernels
  15. Methodology
  16. ...and 16 more sections

Figures (13)

  • Figure 1: Common variations in 2-D DP algorithms in Bioinformatics. Kernels are indexed using #'s based on Table \ref{['table:summary']}.
  • Figure 2: DP-HLS implementation overview. (A) Basic workflow of DP-HLS kernels from user customization to FPGA deployment. (B) Front-end layout of DP-HLS kernels with customizable modules. (C) Key back-end optimizations with corresponding pragma directives.
  • Figure 3: Input alphabet for (Left) DNA sequences and (Right) complex number sequences.
  • Figure 4: Definition of ScoringParams used in (Left) Global Linear kernel (\ref{['kernel:1']}) and (Right) Viterbi kernel (\ref{['kernel:10']}).
  • Figure 5: Definition of traceback states for (Left) Global Affine (\ref{['kernel:2']}) and (Right) Global Two-piece Affine (\ref{['kernel:5']}) kernels.
  • ...and 8 more figures