ZipCache: A DRAM/SSD Cache with Built-in Transparent Compression

TL;DR

ZipCache tackles the practical barrier to using block compression in key-value caches by redesigning the cache architecture around B+ tree indexing and a two-tier DRAM/SSD cache. It leverages three specialized B+ trees to manage tiny, medium, and large objects, and uses mechanisms such as decompression early termination, adaptive compression bypassing, and per-page write buffering on the DRAM tier, alongside intra-SSD hashing and page-aligned eviction on the SSD tier with transparent compression hardware. Experimental results show substantial improvements in throughput and latency, and dramatic reductions in SSD write amplification compared with prior hybrid caches, demonstrating the viability of hardware-assisted, block-based compression for performance-critical caching. The work highlights practical design trade-offs between compression ratio, access latency, and storage/write costs, and suggests a path for broader adoption of block compression in data-center caches with emerging computational SSDs.

Abstract

As a core component in modern data centers, key-value cache provides high-throughput and low-latency services for high-speed data processing. The effectiveness of a key-value cache relies on its ability of accommodating the needed data. However, expanding the cache capacity is often more difficult than commonly expected because of many practical constraints, such as server costs, cooling issues, rack space, and even human resource expenses. A potential solution is compression, which virtually extends the cache capacity by condensing data in cache. In practice, this seemingly simple idea has not gained much traction in key-value cache system design, due to several critical issues: the compression-unfriendly index structure, severe read/write amplification, wasteful decompression operations, and heavy computing cost. This paper presents a hybrid DRAM-SSD cache design to realize a systematic integration of data compression in key-value cache. By treating compression as an essential component, we have redesigned the indexing structure, data management, and leveraged the emerging computational SSD hardware for collaborative optimizations. We have developed a prototype, called ZipCache. Our experimental results show that ZipCache can achieve up to 72.4% higher throughput and 42.4% lower latency, while reducing the write amplification by up to 26.2 times.

Figures (16)

• Figure 1: Comparison of compression ratio, (de)compression latency under different compression block size.
• Figure 2: (a) Compression ratio of 4KB blocks under hash index and B+ tree index, and (b) latency of index traversing and block decompression under different total number of cache objects (hence different B+ tree depth), where key and values are obtained from Bitstamp Exchange Data BTC-link.
• Figure 3: An illustration of (a) an SSD with built-in transparent compression, and (b) the expanded LBA space.
• Figure 4: Overview of ZipCache architecture that employ three B+ trees to manage the DRAM cache tier, SSD cache tier, and large-size cache objects respectively.
• Figure 5: Illustration of hash-based mapping between cache objects and sub-pages in a leaf page of $BT_{DRAM}$, including the leaf page decompression early termination.