Straintronic magnetic tunnel junctions for analog computation: A perspective

TL;DR

The paper addresses the need for analog-dedicated hardware by introducing straintronic magnetic tunnel junctions (s-MTJs), where gate-voltage–generated strain continuously tunes the soft-layer magnetization and hence the resistance between $R_P$ and $R_{AP}$. It develops a linear transfer region in the conductance $G_{s-MTJ} = G_{AP} + \kappa (V_G - \delta)$, with $\kappa$ and $\delta$ governed by device parameters and material constants, and validates linearity via stochastic simulations. The authors demonstrate practical analog computing primitives: a multiplier/divider using the linear conductance, a quasi-analog vector–matrix multiplier requiring only $2N^2$ MTJs, and linear synapses suitable for on-chip learning with symmetric weight updates. They further discuss extending the linear region by increasing $R_{AP}$ and outline the conditions under which s-MTJs outperform memristive and domain-wall-based counterparts, highlighting potential for energy-efficient, scalable analog neural computation.

Abstract

The straintronic magnetic tunnel junction (s-MTJ) is an MTJ whose resistance state can be changed continuously or gradually from high to low with a gate voltage that generates strain the magnetostrictive soft layer. This unusual feature, not usually available in MTJs that are switched abruptly with spin transfer torque, spin-orbit torque or voltage-controlled-magnetic-anisotropy, enables many analog applications where the typically low tunneling magneto-resistance ratio of MTJs (on/off ratio of the switch) and the relatively large switching error rate are not serious impediments unlike in digital logic or memory. More importantly, the transfer characteristic of a s-MTJ (conductance versus gate voltage) always sports a linear region that can be exploited to implement analog arithmetic, vector matrix multiplication and linear synapses in deep learning networks very effectively. In these applications, the s-MTJ is actually superior to the better known memristors and domain wall synapses which do not exhibit the linearity and/or the analog behavior.

Figures (8)

• Figure 1: (a) A magnetic tunnel junction (MTJ). (b) Switching the MTJ resistance with spin transfer torque (STT). (c) Switching the resistance with spin-orbit torque (SOT). (d) Switching the resistance with voltage-controlled-magnetic-anisotropy (VCMA). (d) Straintronic switching. The diagrams are not to scale.
• Figure 2: The net effective magnetic field experienced by the soft layer of a straintronic magnetic tunnel junction in the presence of: (1) strain of the appropriate sign and (2) dipole coupling with the hard layer. ${\bf H}_s$ is the effective magnetic field due to strain and ${\bf H}_d$ is the effective magnetic field due to dipole coupling with the hard layer. By varying ${\bf H}_s$ continuously with a gate voltage, one can vary $\phi$ and hence the resistance of the s-MTJ continuously between $R_P$ and $R_{AP}$.
• Figure 3: (a) A domain wall synapse consisting of a magnetic tunnel junction placed over a heavy metal layer. Successive current pulses passed through the heavy metal exerts successive spin-orbit torques on the soft layer that is in contact with the heavy metal. These pulses move the domain wall in steps thereby changing the fraction of the soft layer whose magnetization is parallel (antiparallel) to that of the hard layer. The resistance of the MTJ is the parallel combination of three resistances consisting of the fraction where the magnetizations of the hard and soft layer are parallel, the fraction where they are antiparallel and the remaining fraction involving the domain wall. (b) A grooved soft layer where the domain wall position is stabilized against "creep" which is back-and-forth motion of the domain wall due to thermal noise.
• Figure 4: The structure of a straintronic magnetic tunnel junction reproduced from jianping with permission of the American Institute of Physics.
• Figure 5: The transfer characteristic of a straintronic magnetic tunnel junction computed with the use of stochastic Landau-Lifshitz-Gilbert simulation of the soft layer's magnetodynamics in the presence of gate-voltage-generated strain at room temperature. This figure is reproduced from matrix-paper with the permission of the Institute of Electrical and Electronics Engineers. The parameters for the soft layer were major axis = 800 nm, minor axis = 700 nm, thickness = 2.2 nm, saturation magnetization $M_s$ = 8.5$\times$10$^5$ A/m, dipole coupling field $H_d$ = 1000 Oe, Gilbert damping constant = 0.1, saturation magnetostriction $\lambda_s$ = 600 ppm, Young's modulus $Y$ = 120 GPa, piezoelectric coefficient $d_{33}$ = 1.5$\times$10$^{-9}$ C/N and the piezoelectric layer thickness $t$ = 1 $\mu$m. The value of $R_{AP}$ was assumed to be 2 k$\Omega$ and the value of $R_P$ was 1 k$\Omega$.