HETRI: Heterogeneous Ising Multiprocessing

TL;DR

This paper addresses the scalability bottleneck of Ising hardware for combinatorial optimization by introducing HETRI, a heterogeneous Ising multiprocessing architecture that combines multiple cores with diverse connectivity onto a single chip. By organizing spins into cores with all-to-all, King’s graph, and hybrid topologies and by matching subproblems to the most suitable core, HETRI aims to reduce problem decomposition and embedding overhead while maintaining the same spin-budget $N_{max}$ per technology. Across QUBO, 3SAT, and Gset benchmarks, HETRI generally matches or outperforms homogeneous designs in time-to-solution and energy-to-solution, with the best gains when problem connectivity aligns with core topology; however, performance can degrade for workloads strongly skewed toward a single connectivity pattern. Overall, the architecture-level insight suggests that diversity in Ising-core connectivity is a practical path to scalable, hardware-efficient Ising solvers for real-world optimization problems, applicable across technologies and compatible with existing decomposition strategies.

Abstract

Ising machines are effective solvers for complex combinatorial optimization problems. The idea is mapping the optimal solution(s) to a combinatorial optimization problem to the minimum energy state(s) of a physical system, which naturally converges to a minimum energy state upon perturbance. The underlying mathematical abstraction, the Ising model, can capture the dynamic behavior of different physical systems by mapping each problem variable to a spin which can interact with other spins. Ising model as a mathematical abstraction can be mapped to hardware using traditional devices. In this paper we instead focus on Ising machines which represent a network of physical spins directly implemented in hardware using, e.g., quantum bits or electronic oscillators. To eliminate the scalability bottleneck due to the mismatch in problem vs. Ising machine size and connectivity, in this paper we make the case for HETRI: Heterogeneous Ising Multiprocessing. HETRI organizes the maximum number of physical spins that the underlying technology supports in Ising cores; and multiple independent Ising cores, in Ising chips. Ising cores in a chip feature different inter-spin connectivity or spin counts to match the problem characteristics. We provide a detailed design space exploration and quantify the performance in terms of time or energy to solution and solution accuracy with respect to homogeneous alternatives under the very same hardware budget and considering the very same spin technology.

Figures (11)

• Figure 1: Representative problem connectivity (variable interaction) graphs: (a) Planar MIS (Maximum Independent Set), (b) 3SAT (Satisfiability), (c) nonplanar MIS. Each dot corresponds to a spin; and each edge, to a non-zero interaction strength. MIS is a graph problem where the goal is to maximize the number of vertices in an independent set, i.e., a set of vertices with no edges connecting its elements. SAT is after finding values of Boolean variables that render a given Boolean formula logic 1. In planar MIS, graph connectivity is limited to nearest neighbors in a mesh. Nonplanar MIS has no limitation.
• Figure 2: Problem connectivity graph capturing problem variable interactions (a), and its (Ising machine) embedding using node replication (b). Each spin corresponds to a node; each edge in (b), to a physical link.
• Figure 3: 6-core Ising multiprocessor design space with homogeneous vs. heterogeneous cores.
• Figure 4: % problems that can be embedded into an Ising core with King's graph connectivity, as a function of problem density (as a proxity for problem connectivity) and problem size in terms of logical number of spins $N = N_{logical}$.
• Figure 5: Subproblems of a representative 25-variable 3SAT problem that can(not) be embedded into an Ising core with King's graph connectivity, as a function of density and subproblem size, denoted in green (red).