Hybrid cat-transmon architecture for scalable, hardware-efficient quantum error correction

TL;DR

The paper proposes a hardware-efficient quantum error-correcting architecture that hybrids dissipatively stabilized cat qubits as data qubits with transmon ancillas for syndrome extraction. It introduces a cat-transmon CR_X gate to correct residual cat X errors while preserving a large Z/X noise bias, enabling the use of rectangular surface codes with reduced qubit overhead. Numerical analysis shows biases in the range of $10^3$–$10^4$ and infidelities around $10^{-3}$ are achievable with state-of-the-art parameters, making memory overhead competitive with unbiased architectures at physical error rates around $10^{-5}$–$10^{-4}$. The work highlights practical gate design—relying on native dispersive couplings and pulsed stabilization—that could enable near-term demonstrations and suggests future directions, including alternative ancilla candidates and LDPC or lattice-surgery strategies to further boost efficiency and scalability.

Abstract

Dissipative cat qubits are a promising physical platform for quantum computing, since their large noise bias can enable more hardware-efficient quantum error correction. In this work we theoretically study the long-term prospects of a hybrid cat-transmon quantum computing architecture where dissipative cat qubits play the role of data qubits, and error syndromes are measured using ancillary transmon qubits. The cat qubits' noise bias enables more hardware-efficient quantum error correction, and the use of transmons allows for practical, high-fidelity syndrome measurement. While correction of the dominant cat Z errors with a repetition code has recently been demonstrated in experiment, here we show how the architecture can be scaled beyond a repetition code. In particular, we propose a cat-transmon entangling gate that enables the correction of residual cat X errors in a thin rectangular surface code, so that logical error can be arbitrarily suppressed by increasing code distance. We numerically estimate logical memory performance, finding significant overhead reductions in comparison to architectures without biased noise. For example, with current state-of-the-art coherence, physical error rates of $10^{-3}$ and noise biases in the range $10^{3} - 10^{4}$ are achievable. With this level of performance, the qubit overhead required to reach algorithmically-relevant logical error rates with the cat-transmon architecture matches that of an unbiased-noise architecture with physical error rates in the range $10^{-5} - 10^{-4}$.

Figures (17)

• Figure 1: Hybrid dissipative cat-transmon QEC architecture. (a) Cat-transmon unit cell. Dissipatively stabilized cats act as data qubits, and transmons are employed to extract error syndromes. The cats and transmons are coupled via tunable dispersive couplings. (b) Surface codes built from the cat-transmon unit cell. By constructing rectangular codes that offer more protection against the cats' dominant $Z$ errors than their suppressed $X$ errors, the cats' biased noise can allow for more hardware-efficient error correction. (c) Syndrome measurement circuits. To measure $X$-type syndromes, transmon-controlled $\text{CX}$ gates are implemented using the native dispersive couplings. To measure $Z$-type syndromes, the architecture employs a proposed cat-controlled entangling gate, termed $\text{CR}_\text{X}$. To prevent leakage out of the cat-qubit code space, engineered dissipation is applied to the cats during the transmon ancilla readout and reset steps (indicated by boxes labelled “$\mathcal{D}$”).
• Figure 2: Simplified schematic of the $\text{CR}_\text{X}$ gate. To implement the cat-controlled transmon rotation, the cat is first displaced by $+\alpha$, such that $\ket{-\alpha}\to\ket{0}$. A number-selective drive is then applied to the transmon, with the drive frequency resonant with the transmon frequency when the storage is in vacuum. The storage mode is subsequently displaced back, and the net effect is a rotation of the transmon that occurs only if the cat was initially in $\ket{-\alpha}$. Note that this simplified diagram neglects transmon-dependent rotation of the storage mode during the selective pulse due to the dispersive coupling.
• Figure 3: Storage "echo" to mitigate dephasing-induced phase flips during the $\text{CR}_\text{X}$ gate. (a) Without the echo displacement, spurious rotations in a displaced cat can result in parity flips (cat $Z$ errors) once displaced back, graphically indicated by the positioning of the red interference fringe at the origin in the right diagram. (b) To mitigate these $Z$ errors, an “echo displacement” is applied in between successive selective pulses, such that the cat spends equal time on the left and right halves of phase space. (c) The final probability of a cat Z error is plotted as a function of the storage dephasing strength for both white and $1/f$ dephasing noise. The inclusion of the storage echo significantly reduces the error probability for the low-frequency dominated $1/f$ noise, but not for white noise. Markers indicate trajectory simulation results, and solid lines are analytical predictions. See \ref{['App:storage_echo']} for derivations and numerical details.
• Figure 4: Mitigating $\text{CR}_\text{X}$ coherent error with pulse shaping. (a) Frequency spectra of standard and shaped pulses. The shaped DRAG pulse is designed to minimize spectral content at the frequency of the transmon when $|2\alpha|^2$ photons are in the storage, i.e. $\omega_q+2|\alpha|^2 \chi$, where $\omega_q$ is the unshifted transmon frequency. To guide the eye, the photon number distribution for the coherent state $|2\alpha\rangle$ is plotted (on a linear scale, not shown), with $|\braket{2\alpha|n}|^2$ positioned at $\omega_q+n\chi$ on the horizontal axis. At the frequencies where $|2\alpha\rangle$ has significant support, the spectral content of the DRAG pulse is significantly suppressed relative to the case without DRAG. (b) Coherent error reduction for via DRAG. The coherent error of different selective pulse ansatzes is plotted as a function of $|\alpha|^2$, where at each point the free parameters of a pulse ansatz are optimized to minimize coherent error. The coherent error is computed as the average gate infidelity of the Pauli error channel extracted from simulations of the $\text{CR}_\text{X}$ gate without decoherence (see \ref{['app:extracting_error_channels']}).
• Figure 5: Error and bias of transmon-controlled $\text{CX}$ (top row) and cat-controlled $\text{CR}_\text{X}$ (bottom row) gates. Pauli error channels are extracted from master equation simulations of the gates, and the resultant (a) average gate infidelity, (b) cat bit-flip probability, and (c) cat noise bias are plotted as a function of $q$ (which specifies the decoherence rates of the cat and transmon per \ref{['tab:noise_model']}) and $|\alpha|^2$.