KALAM: toolKit for Automating high-Level synthesis of Analog computing systeMs

TL;DR

KALAM (toolKit for Automating high-Level synthesis of Analog computing systeMs), which leverages factor graphs as the foundational paradigm for synthesizing MP-based analog computing systems and demonstrates KALAM's versatility for tasks such as Bayesian inference, Low-Density Parity Check (LDPC) decoding, and Artificial Neural Networks (ANN).

Abstract

Diverse computing paradigms have emerged to meet the growing needs for intelligent energy-efficient systems. The Margin Propagation (MP) framework, being one such initiative in the analog computing domain, stands out due to its scalability across biasing conditions, temperatures, and diminishing process technology nodes. However, the lack of digital-like automation tools for designing analog systems (including that of MP analog) hinders their adoption for designing large systems. The inherent scalability and modularity of MP systems present a unique opportunity in this regard. This paper introduces KALAM (toolKit for Automating high-Level synthesis of Analog computing systeMs), which leverages factor graphs as the foundational paradigm for synthesizing MP-based analog computing systems. Factor graphs are the basis of various signal processing tasks and, when coupled with MP, can be used to design scalable and energy-efficient analog signal processors. Using Python scripting language, the KALAM automation flow translates an input factor graph to its equivalent SPICE-compatible circuit netlist that can be used to validate the intended functionality. KALAM also allows the integration of design optimization strategies such as precision tuning, variable elimination, and mathematical simplification. We demonstrate KALAM's versatility for tasks such as Bayesian inference, Low-Density Parity Check (LDPC) decoding, and Artificial Neural Networks (ANN). Simulation results of the netlists align closely with software implementations, affirming the efficacy of our proposed automation tool.

Figures (4)

• Figure 1: This figure shows the proposed flow of KALAM for synthesizing analog MP-based systems. The associated figures in each stage refer to the design of a Bayesian network for illustration. Stage$1$ of this figure shows the factor graph representation to be synthesized. This factor graph is translated into a computational graph in Stage$2$, which is then mapped onto analog circuits in Stage$3$. The MP-based analog standard cell library is input at Stage$3$. Finally, the corresponding netlist is then generated in Stage$4$ and validated for accuracy through functional simulation in Stage$5$.
• Figure 2: This figure is an example illustration of the different synthesis stages for a Bayesian DAG using its input probabilities. It is first translated into a factor graph. A computational graph is then generated with respect to the computations of each factor node after variable elimination. Optimization strategies such as Boolean simplification and precision tuning are employed before generating the final optimized analog map.
• Figure 3: Layout for the KALAM-generated netlist corresponding to the Computational Graph in Fig. \ref{['case_study']} consisting of eight Soft-AND gates (each mapped to a multiplier), using the place-and-route options offered by Cadence Layout GXL. The inset figure zooms into the layout of a single Soft-AND gate.
• Figure 4: \ref{['tanner']} Tanner Graph for a (32,8) LDPC Decoder; \ref{['ber']} Bit Error Rate (BER) and \ref{['fer']} Frame Error Rate (FER) of the simulated netlist w.r.t. the software implementation for code lengths $32-$bit (synthesis runtime$=32 ms$), $64-$bit (synthesis runtime$=39 ms$) and $96-$bit (synthesis runtime$=51 ms$).