Online Alignment and Addition in Multi-Term Floating-Point Adders

TL;DR

Experimental results show that employing the proposed align-and-add operators for the implementation of multiterm floating-point adders can improve delay or save significant area and power.

Abstract

Multi-term floating-point addition appears in vector dot-product computations, matrix multiplications, and other forms of floating-point data aggregation. A critical step in multi-term floating point addition is the alignment of fractions of the floating-point terms before adding them. Alignment is executed serially by identifying first the maximum of all exponents and then shifting the fraction of each term according to the difference of its exponent from the maximum one. Contrary to common practice, this work proposes a new online algorithm that splits the identification of the maximum exponent, the alignment shift for each fraction, and their addition to multiple fused incremental steps that can be computed in parallel. Each fused step is implemented by a new associative operator that allows the incremental alignment and addition for arbitrary number of operands. Experimental results show that employing the proposed align-and-add operators for the implementation of multi-term floating point adders can improve delay or save significant area and power. The achieved area and power savings range between 3%-23% and 4%-26%, respectively.

Figures (5)

• Figure 1: Baseline approach for multi-term fraction alignment and addition.
• Figure 2: Tree-based organization of parallel alignment and addition for an 8-term floating point addition using (a) the radix-2 $\circledcirc$ operator in all nodes of the tree and (b) a mixture of radix-4 and radix-2 operators.
• Figure 3: Structure of commonly used FP data types.
• Figure 4: The a) area and b) average power of 32-term BFloat16 adders designed with the baseline approach and the proposed approach that uses the newly introduced align-and-add operator $\circledcirc$ in various mixed-radix configurations.
• Figure 5: The most area efficient designs achieved by each configuration for 32-term BFloat16 for various clock period targets using 1--4 pipeline stages.