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A Host-SSD Collaborative Write Accelerator for LSM-Tree-Based Key-Value Stores

KiHwan Kim, Hyunsun Chung, Seonghoon Ahn, Junhyeok Park, Safdar Jamil, Hongsu Byun, Myungcheol Lee, Jinchun Choi, Youngjae Kim

TL;DR

This study proposes KVACCEL, a novel hardware-software co-design framework that eliminates write stalls by leveraging a dual-interface SSD, and shows that for write-intensive workloads, KVACCEL outperforms ADOC in terms of throughput and performance-to-CPU-utilization efficiency.

Abstract

Log-Structured Merge (LSM) tree-based Key-Value Stores (KVSs) are widely adopted for their high performance in write-intensive environments, but they often face performance degradation due to write stalls during compaction. Prior solutions, such as regulating I/O traffic or using multiple compaction threads, can cause unexpected drops in throughput or increase host CPU usage, while hardware-based approaches using FPGA, GPU, and DPU aimed at reducing compaction duration introduce additional hardware costs. In this study, we propose KVACCEL, a novel hardware-software co-design framework that eliminates write stalls by leveraging a dual-interface SSD. KVACCEL allocates logical NAND flash space to support both block and key-value interfaces, using the key-value interface as a temporary write buffer during write stalls. This strategy significantly reduces write stalls, optimizes resource usage, and ensures consistency between the host and device by implementing an in-device LSM-based write buffer with an iterator-based range scan mechanism. Our extensive evaluation shows that for write-intensive workloads, KVACCEL outperforms ADOC by up to 1.17x in terms of throughput and performance-to-CPU-utilization efficiency. For mixed read-write workloads, both demonstrate comparable performance.

A Host-SSD Collaborative Write Accelerator for LSM-Tree-Based Key-Value Stores

TL;DR

This study proposes KVACCEL, a novel hardware-software co-design framework that eliminates write stalls by leveraging a dual-interface SSD, and shows that for write-intensive workloads, KVACCEL outperforms ADOC in terms of throughput and performance-to-CPU-utilization efficiency.

Abstract

Log-Structured Merge (LSM) tree-based Key-Value Stores (KVSs) are widely adopted for their high performance in write-intensive environments, but they often face performance degradation due to write stalls during compaction. Prior solutions, such as regulating I/O traffic or using multiple compaction threads, can cause unexpected drops in throughput or increase host CPU usage, while hardware-based approaches using FPGA, GPU, and DPU aimed at reducing compaction duration introduce additional hardware costs. In this study, we propose KVACCEL, a novel hardware-software co-design framework that eliminates write stalls by leveraging a dual-interface SSD. KVACCEL allocates logical NAND flash space to support both block and key-value interfaces, using the key-value interface as a temporary write buffer during write stalls. This strategy significantly reduces write stalls, optimizes resource usage, and ensures consistency between the host and device by implementing an in-device LSM-based write buffer with an iterator-based range scan mechanism. Our extensive evaluation shows that for write-intensive workloads, KVACCEL outperforms ADOC by up to 1.17x in terms of throughput and performance-to-CPU-utilization efficiency. For mixed read-write workloads, both demonstrate comparable performance.

Paper Structure

This paper contains 24 sections, 1 equation, 14 figures, 6 tables.

Table of Contents

  1. Introduction
  2. Background and Related Work
  3. Log-Structured Merge Tree and Write Stall Issue
  4. Existing Optimizations for Addressing Write Stall Issue
  5. Problem Definition
  6. Slowdowns: The Inefficient Write Stall Solution
  7. Underutilized PCIe Bandwidth and Device Resources
  8. Exploring Available I/O Processing Capacity of the SSD
  9. Opportunities in Key-Value Interfaces
  10. Design of KVAccel
  11. Design Goals
  12. Overall Architecture
  13. Interface Pathing via Software Modules
  14. Hybrid Dual-Interface SSD
  15. Rollback Operation
  16. ...and 9 more sections

Figures (14)

  • Figure 1: An architecture of LSM-tree.
  • Figure 2: Per-second throughput time-series for RocksDB and ADOC, based on write slowdown usage.
  • Figure 3: Throughput (a) and tail latency (b) results of RocksDB and ADOC, based on write slowdown usage.
  • Figure 4: Measurements of PCIe bandwidth utilization in the 100–200 seconds of execution range in RocksDB without applying slowdown techniques.
  • Figure 5: A Cumulative Distribution Function (CDF) of PCIe bandwidth during a period of write stall on RocksDB. The numbers on the legend denote compaction thread count.
  • ...and 9 more figures