Scaling Effects of Transistor Leakage Current and IR Drop on 1T1R Memory Arrays

TL;DR

An optimal resistance range of memristor devices exists for good array scaling capability, where the transistor read resistance and the IR drop issue establish a lower resistance boundary, while the transistor leakage issue sets an upper resistance boundary.

Abstract

1T1R (1-transistor-1-resistor) memory crossbar arrays represent a promising solution for compute-in-memory matrix-vector multiplication accelerators and embedded or storage-class memory. However, the size and scaling of these arrays are hindered by critical challenges, such as the IR drop on metal lines and the accumulation of leakage current from the transistors. Although the IR drop issue has been extensively investigated, the impact of transistor leakage current has received limited attention. In this work, we investigate both issues and highlight how transistor leakage in 1T1R arrays has effects similar to IR drop, which degrades the memory cell sensing margin, especially as the technology node scales down. This degradation could pose reliability concerns, particularly where the on/off ratio or sensing margin of memristors is critical. We characterized the joint effects of transistor read resistance, transistor leakage current, and IR drop as the array size scales up and the fabrication node scales down. Based on a model developed using specifications of a 22nm FDSOI technology, we found that an optimal resistance range of memristors exists for good array scaling capability, where the transistor read resistance and the IR drop issue establish a lower resistance boundary, while the transistor leakage issue sets an upper resistance boundary. This work provides valuable scaling guidelines for engineering the properties of memristor devices in 1T1R memory arrays.

Figures (6)

• Figure 1: Illustration of non-ideal factors, including metal line resistance and transistor leakage current, in 1T1R arrays for various applications where sensing margin is critical: (a) Preventing signal transmission errors in memristor-based crossbar routers (i.e., switch matrices), which are used to transmit signals between neural computing cores in multi-core spiking neural network (SNN) neuromorphic chips dalgaty2024mosaic2023chenchen2022reliability. (b) Avoiding bit flips during memory cell sensing in embedded memory or storage class memory (SCM) designs. The IR drop issue has been extensively studied while the the transistor leakage current gained limited attention.
• Figure 2: The model of one column in 1T1R crossbar array when sensing a memory cell including parasitic metal line resistance and transistor leakage current. Assuming $n > j > i$. Each transistor which is turned off contributes $I_{Tleak}$, while which is turned on contributes $R_T$ in serial with the resistance of the memristor. (a) The overall read current $I_{on}$ when sensing $R_{on}$. (b) The overall read current $I_{off}$ when sensing $R_{off}$. (c) The physical view of 1T1R cell that depicts the metal line resistance and the transistor leakage current.
• Figure 3: Impact of metal line IR drop and transistor leakage currents on the effective sensing margin of memory cells as the array size increases from 64 to 4096 ($N_r$ denotes $n$ in Eq. \ref{['eq:k_p']}). (a) IR drop degrades the effective on/off ratio (sensing margin), with $V_{read}$ is 0.2V. Higher resistance values ($R_{on}$) mitigate the effect of IR drop. (b) Transistor leakage in 1T1R arrays similarly degrades the sensing margin. In contrast to IR drop, higher resistance boosts the effect of transistor leakage and worsens the sensing margin. The influence of $R_T$ is also annotated. (c) The combined scaling effects of IR drop and transistor leakage. When both factors are considered, the optimal resistance for size scaling shifts, highlighting potential trade-offs are involved in array size scaling.
• Figure 4: (a) For optimal array size scaling while maintaining a high sensing margin, $20k\Omega<R_{on}<150 k\Omega$ is ideal (at $k = 10$). The mathematical model matches the circuit simulations very well. Each red data point corresponds to a circuit simulation. (b) The size scaling effect at $k=100$.
• Figure 5: Detailed scaling effects illustration of $R_T$, $r$ and $I_{Tleak}$, using the model of $N_r=1024$ in Fig. \ref{['fig:best_R']} (a) in 22nm node. As the CMOS technology node scales down, IR drop and transistor leakage will influence more. The scaling trend of sensing margin degradation as technology node scales down will be similar to that of size scaling up.