MPLS Network Actions: Technological Overview and P4-Based Implementation on a High-Speed Switching ASIC

TL;DR

The paper surveys the MPLS Network Actions (MNA) framework and demonstrates a first hardware realization (P4-MNA) on Intel Tofino 2 that achieves $400$ Gb/s per port while processing up to $32$ network actions within NAS-encoded stacks. It validates two tangible network actions—Alternate Marking Method (AMM) for loss measurement and network slicing for bandwidth reservations—through a line-rate testbed and controlled experiments, showing negligible per-hop latency increase. The work analyzes structural constraints for header stacking (RLD and NAS sizes), proposes signaling of hardware capabilities to enable heterogeneous deployments, and discusses ISD versus PSD approaches for mutable data, along with security considerations for MNA. Collectively, the findings support MNA as a viable, hardware-feasible path for MPLS extensions in high-speed networks, with practical guidance for deployment and future enhancements.

Abstract

In MPLS, packets are encapsulated with labels that add domain-specific forwarding information. Special purpose labels were introduced to trigger special behavior in MPLS nodes but their number is limited. Therefore, the IETF proposed the MPLS Network Actions (MNA) framework. It extends MPLS with new features, some of which have already been defined to support relevant use cases. This paper provides a comprehensive technological overview of MNA concepts and use cases. It compares MNA to IPv6 extension headers (EHs) that serve a similar purpose, and argues that MNA can be better deployed than EHs. It then presents P4-MNA, a first hardware implementation running at 400 Gb/s per port. Scalability and performance of P4-MNA are evaluated, showing negligible impact on processing delay caused by network actions. Moreover, the applicability of MNA is demonstrated by implementing the use cases of link-specific packet loss measurement using the alternate-marking-method (AMM) and bandwidth reservation using network slicing. We identify header stacking constraints resulting from hardware resources and from the number of network actions that must be supported according to the MNA encoding. They make an implementation for hardware that can only parse a few MPLS headers infeasible. We propose to make the number of supported network actions a node parameter and signal this in the network. Then, an upgrade to MNA is also feasible for hardware with fewer available resources. We explain that for MNA with in-stack data (ISD), some header bits must remain unchanged during forwarding, and give an outlook on post-stack data (PSD).

Figures (27)

• Figure 1: MPLS forwarding using virtual circuits and SR-MPLS.
• Figure 2: The MPLS label stack is located between the Layer 2 header and the Layer 3 header. An MPLS stack consists of one or more LSE, each of which consists of a label value, a traffic class (TC), a bottom of stack bit (S), and a time-to-live (TTL) field.
• Figure 3: MPLS label stacks containing bSPL and eSPL LSErfc9017.
• Figure 4: An example of two NAS inserted into an MPLS label stack. A NAS consists of at least two LSE and up to 17 LSE.
• Figure 5: The four different LSE encodings of a NAS in the MNA framework.