Efficient Frequency Allocation for Superconducting Quantum Processors Using Improved Optimization Techniques

TL;DR

This work tackles frequency allocation for fixed-frequency superconducting qubits, where fabrication dispersion causes frequency collisions and reduces yield. It extends prior optimization by tightening constraints, introducing edgewise differences, optimizing edge orientation, and enabling multimodule boundary-aware design to scale to large processors. The combined methods raise the feasible dispersion threshold to about $6.5$ MHz and achieve yields above $10$ percent on large chips (e.g., square grids with thousands of qubits), while demonstrating practical scalability through multimodule assembly and open-source models. The approach offers a path toward more scalable, collision-robust quantum processors and can inform hardware designs and future optimization for broader platforms.

Abstract

Building on previous research on frequency allocation optimization for superconducting circuit quantum processors, this work incorporates several new techniques to improve overall solution quality. New features include tightening constraints, imposing edgewise differences, including edge orientation in the optimization, and integrating multimodule designs with various boundary conditions. These enhancements allow for greater flexibility in processor design by eliminating the need for handpicked orientations. We support the efficient assembly of large processors with dense connectivity by choosing the best boundary conditions. Examples demonstrate that, at low computational cost, the new optimization approach finds a frequency configuration for a square chip with over 1,000 qubits and over 10% yield at much larger dispersion levels than required by previous approaches.

Figures (6)

• Figure 1: Yield at dispersion of 10 MHz for different orientations. (a) The optimized objective and yield for $4\times 4$ square (s) grid (b1) and 6-ring hexagon (h) grid (b2). Green solid box: 4$\times$4 square grid using the orientation in Ref. morvan2022optimizing; red open box: 4$\times$4 square grid using random orientations; blue open hexagon: 6-ring hexagon grid using random orientations.
• Figure 2: Tested boundary conditions: (a) conventional periodic boundary condition (PBC1); (b) and (c): twisted boundary conditions (PBC2 and PBC3); (d) Möbius boundary condition (MBC1); (e) and (f): twisted Möbius boundary condition (MBC2 and MBC3).
• Figure 3: (a) Yield at dispersion level of $\sigma$=10 MHz for two sets of orientation, with constraint tolerance added in unit of $\sigma$, as discussed in the text. (b1) and (b2): Preset orientations of the $4\times 4$ grid. The sudden drop in yield observed in the (b2) curves is caused by the emergence of a different type of constraint violation during frequency reoptimization, as discussed in the main text.
• Figure 4: (a) Yield at different levels of dispersion for different sets of orientation. Red: the orientation used in Ref. morvan2022optimizing; grey: results from 10 random sets of orientation; blue solid: result with orientation optimization and enforced edge differences (as in \ref{['eq:diff']}). (b) Grey: results from 10 random sets of orientation; blue solid: result with orientation optimization and enforced edge differences. In both graphs, the insets give the optimized orientation. All solid curves are optimized with constraint tolerance of 10 MHz, while the dashed curves indicate results with orientation optimization, edge differences imposed and larger constraint tolerance (20 MHz).
• Figure 5: (a) Performance of local $4\times 4$ modules: the local yield at different levels of dispersion for different sets of periodic boundary conditions. Green line: effective yield of 96.5%; Blue line: dispersion of 5 MHz. Inset: optimal frequency configuration for the best boundary condition [PBC3 in \ref{['fig:pbc']}]. (b) Assembling a $8\times 8$ chip: red: directly optimizing a $8\times 8$ chip; others: assembling $4\times 4$ chips to a $8\times 8$ chip.