Energy Efficient Dual Designs of FeFET-Based Analog In-Memory Computing with Inherent Shift-Add Capability

TL;DR

A FeFET based IMC paradigm that performs partial MAC in each column, and inherently integrates the shift-add process for 4-bit weights by leveraging FeFET’s analog storage characteristics is introduced.

Abstract

In-memory computing (IMC) architecture emerges as a promising paradigm, improving the energy efficiency of multiply-and-accumulate (MAC) operations within DNNs by integrating the parallel computations within the memory arrays. Various high-precision analog IMC array designs have been developed based on both SRAM and emerging non-volatile memories. These designs perform MAC operations of partial input and weight, with the corresponding partial products then fed into shift-add circuitry to produce the final MAC results. However, existing works often present intricate shift-add process for weight. The traditional digital shift-add process is limited in throughput due to time-multiplexing of ADCs, and advancing the shift-add process to the analog domain necessitates customized circuit implementations, resulting in compromises in energy and area efficiency. Furthermore, the joint optimization of the partial MAC operations and the weight shift-add process is rarely explored. In this paper, we propose novel, energy efficient dual designs of FeFET based high precision analog IMC featuring inherent shift-add capability. We introduce a FeFET based IMC paradigm that performs partial MAC in each column, and inherently integrates the shift-add process for 4-bit weights by leveraging FeFET's analog storage characteristics. This paradigm supports both 2's complement mode and non-2's complement mode MAC, thereby offering flexible support for 4-/8-bit weight data in 2's complement format. Building upon this paradigm, we propose novel FeFET based dual designs, CurFe for the current mode and ChgFe for the charge mode, to accommodate the high precision analog domain IMC architecture.Evaluation results at circuit and system levels indicate that the circuit/system-level energy efficiency of the proposed FeFET-based analog IMC is 1.56$\times$/1.37$\times$ higher when compared to SOTA analog IMC designs.

Figures (12)

• Figure 1: (a)/ (b) Structure of nFeFET/pFeFET. (c) Measured $I_{D}$-$V_{G}$ characteristics with MLC $V_{th}$ states of a fabricated nFeFET.
• Figure 2: (a) Structure of the proposed CurFe architecture. (b) Structure of H4B with TGs. (c) Structure of L4B with TGs and TIA. (d) 1nFeFFET1R structure for $cell_{7}$. (e) 1nFeFFET1R structure for $cell_{0}$-$cell_{6}$. (f) Id-Vg curves of $cell_{0}$-$cell_{7}$. (g) Input bit-serial based MAC with two parts in H4B and L4B.
• Figure 3: Multiplication example of an 1-bit input and 8-bit signed weight in CurFe. The 8-bit weight is divided into (a) high 4-bit and (b) low 4-bit parts in H4B and L4B, respectively. (c) Transient simulation waveforms of this operation.
• Figure 4: (a) Structure of the proposed ChgFe architecture. (b) Structure of H4B with PCTs ans TGs. (c) Structure of L4B with capacitors and TGs. (d) 1pFeFET structure for $cell_{7}$. (e) 1nFeFET structure for $cell_{0}$-$cell_{6}$.
• Figure 5: (a) Id-Vg curves of $cell_{7}$ in ChgFe. (b) Id-Vg curves of $cell_{0}$-$cell_{6}$ in ChgFe.