FeBiM: Efficient and Compact Bayesian Inference Engine Empowered with Ferroelectric In-Memory Computing

TL;DR

FeBiM is proposed, an efficient and compact Bayesian inference engine powered by multi-bit ferroelectric field-effect transistor (FeFET)-based IMC that effectively encodes the trained probabilities of a Bayesian inference model within a compact FeFET-based crossbar.

Abstract

In scenarios with limited training data or where explainability is crucial, conventional neural network-based machine learning models often face challenges. In contrast, Bayesian inference-based algorithms excel in providing interpretable predictions and reliable uncertainty estimation in these scenarios. While many state-of-the-art in-memory computing (IMC) architectures leverage emerging non-volatile memory (NVM) technologies to offer unparalleled computing capacity and energy efficiency for neural network workloads, their application in Bayesian inference is limited. This is because the core operations in Bayesian inference differ significantly from the multiplication-accumulation (MAC) operations common in neural networks, rendering them generally unsuitable for direct implementation in most existing IMC designs. In this paper, we propose FeBiM, an efficient and compact Bayesian inference engine powered by multi-bit ferroelectric field-effect transistor (FeFET)-based IMC. FeBiM effectively encodes the trained probabilities of a Bayesian inference model within a compact FeFET-based crossbar. It maps quantized logarithmic probabilities to discrete FeFET states. As a result, the accumulated outputs of the crossbar naturally represent the posterior probabilities, i.e., the Bayesian inference model's output given a set of observations. This approach enables efficient in-memory Bayesian inference without the need for additional calculation circuitry. As the first FeFET-based in-memory Bayesian inference engine, FeBiM achieves an impressive storage density of 26.32 Mb/mm$^{2}$ and a computing efficiency of 581.40 TOPS/W in a representative Bayesian classification task. These results demonstrate 10.7$\times$/43.4$\times$ improvement in compactness/efficiency compared to the state-of-the-art hardware implementation of Bayesian inference.

Figures (8)

• Figure 1: (a) Schematic of a FeFET device. (b) Partial polarization switching in an MFM capacitor induced by a write pulse train. (c) The multi-level $I_{D}$-$V_{G}$ characteristics. Each dark curve represents a FeFET state.
• Figure 2: The overall workflow of FeBiM. Trained probabilities of the Bayesian model are quantized and mapped to discrete FeFET states. Given observed evidence values, the FeFET-based crossbar outputs maximum posterior.
• Figure 3: The proposed crossbar array effectively programs the priors and likelihoods in multi-bit FeFET cells. During inference, the posteriors are naturally calculated on each $WL$ and fed into the WTA circuit, which detects the maximum posterior.
• Figure 4: (a) Truncated probabilities $P$ are first converted to the logarithmic values and normalized to $P^{\prime}$, which is then quantized and mapped to discrete FeFET states. (b) Relation between the gate pulse number and the FeFET state.
• Figure 5: When varying $P^{\prime}$ stored in two FeFETs, the (a) calculated $I_{WL}$ matches the (b) simulated $I_{WL}$ precisely. (c) Transient simulation of the WTA circuit validates its function.