Logo
ScienceStack
Table of Contents
Fetching ...
Sign In

LLM-Aided Efficient Hardware Design Automation

Kangwei Xu, Ruidi Qiu, Zhuorui Zhao, Grace Li Zhang, Ulf Schlichtmann, Bing Li

TL;DR

Hardware description language (HDL) generation, code debugging, design verification, and physical implementation are discussed, covering hardware description language (HDL) generation, code debugging, design verification, and physical implementation.

Abstract

With the rapidly increasing complexity of modern chips, hardware engineers are required to invest more effort in tasks such as circuit design, verification, and physical implementation. These workflows often involve continuous modifications, which are labor-intensive and prone to errors. Therefore, there is an increasing need for more efficient and cost-effective Electronic Design Automation (EDA) solutions to accelerate new hardware development. Recently, large language models (LLMs) have made significant advancements in contextual understanding, logical reasoning, and response generation. Since hardware designs and intermediate scripts can be expressed in text format, it is reasonable to explore whether integrating LLMs into EDA could simplify and fully automate the entire workflow. Accordingly, this paper discusses such possibilities in several aspects, covering hardware description language (HDL) generation, code debugging, design verification, and physical implementation. Two case studies, along with their future outlook, are introduced to highlight the capabilities of LLMs in code repair and testbench generation. Finally, future directions and challenges are highlighted to further explore the potential of LLMs in shaping the next-generation EDA

LLM-Aided Efficient Hardware Design Automation

TL;DR

Hardware description language (HDL) generation, code debugging, design verification, and physical implementation are discussed, covering hardware description language (HDL) generation, code debugging, design verification, and physical implementation.

Abstract

With the rapidly increasing complexity of modern chips, hardware engineers are required to invest more effort in tasks such as circuit design, verification, and physical implementation. These workflows often involve continuous modifications, which are labor-intensive and prone to errors. Therefore, there is an increasing need for more efficient and cost-effective Electronic Design Automation (EDA) solutions to accelerate new hardware development. Recently, large language models (LLMs) have made significant advancements in contextual understanding, logical reasoning, and response generation. Since hardware designs and intermediate scripts can be expressed in text format, it is reasonable to explore whether integrating LLMs into EDA could simplify and fully automate the entire workflow. Accordingly, this paper discusses such possibilities in several aspects, covering hardware description language (HDL) generation, code debugging, design verification, and physical implementation. Two case studies, along with their future outlook, are introduced to highlight the capabilities of LLMs in code repair and testbench generation. Finally, future directions and challenges are highlighted to further explore the potential of LLMs in shaping the next-generation EDA

Paper Structure

This paper contains 10 sections, 4 figures.

Table of Contents

  1. Introduction
  2. State of the Art of LLM Applications in EDA
  3. Case Study of LLMs in EDA Design Flow
  4. LLM-Aided C/C++ Code Repair for HLS
  5. LLM-Aided TestBench Generation for HDL Design
  6. Design of the driver
  7. Design of the checker
  8. Self-Enhancement
  9. Future Directions and challenges
  10. Conclusion

Figures (4)

  • Figure 1: Typical chip design flow and potential LLM applications.
  • Figure 2: HLS repair using LLM in b5.0 with an LLM-aided code repair framework for HLS (top) and an example of using RAG to repair the recursion error (bottom).
  • Figure 3: AutoBench: Automatic testbench generation workflow for HDL design b8.
  • Figure 4: LLM-Powered intelligent EDA agent.